RW

Richard K. Williams

AI Advanced Analogic Technologies Incorporated: 137 patents #1 of 28Top 4%
SI Siliconix Incorporated: 98 patents #1 of 125Top 1%
GS Gem Services: 35 patents #3 of 19Top 20%
AB Adventive Ip Bank: 11 patents #1 of 2Top 50%
AB Applied Biophotonics: 8 patents #1 of 6Top 20%
LI Listat: 6 patents #1 of 3Top 35%
SS Skyworks Solutions: 5 patents #290 of 948Top 35%
MC Material Science Co.: 3 patents #13 of 75Top 20%
MC Madison Chemcial Co.: 1 patents #3 of 5Top 60%
BL Birchwood Laboratories: 1 patents #5 of 13Top 40%
AD Avery Dennison: 1 patents #568 of 1,021Top 60%
📍 Cupertino, CA: #6 of 6,989 inventorsTop 1%
🗺 California: #203 of 386,348 inventorsTop 1%
Overall (All Time): #1,133 of 4,157,543Top 1%
316
Patents All Time

Issued Patents All Time

Showing 201–225 of 316 patents

Patent #TitleCo-InventorsDate
D467560 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-12-24
D467231 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-12-17
6476442 Pseudo-Schottky diode Robert Blattner 2002-11-05
D465207 Leadframe matrix for a surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-11-05
6465110 Metal felt laminate structures Daniel E. Boss, Scott R. Dobrusky 2002-10-15
6452802 Symmetrical package for semiconductor die Allen K. Lam, Alex K. Choi 2002-09-17
D462062 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-08-27
D461783 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-08-20
D461784 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-08-20
D461459 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-08-13
D461170 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-08-06
D461172 Surface mount package James Harnden, Anthony Chia, Chu Weibing 2002-08-06
6413822 Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer Wayne B. Grabowski 2002-07-02
6307755 Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die Allen K. Lam, Alexander Choi 2001-10-23
6291298 Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses Wayne B. Grabowski 2001-09-18
6277695 Method of forming vertical planar DMOSFET with self-aligned contact Sung-Shan Tai, Dorman C. Pitzer, Wayne B. Grabowski, Anthony C. Tsui, Mike F. Chang 2001-08-21
6268242 Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact Wayne B. Grabowski 2001-07-31
6256200 Symmetrical package for semiconductor die Allen K. Lam, Alex K. Choi 2001-07-03
6239463 Low resistance power MOSFET or other device containing silicon-germanium layer Mohamed N. Darwish, Wayne B. Grabowski, Michael E. Cornell 2001-05-29
6204533 Vertical trench-gated power MOSFET having stripe geometry and high cell density Wayne B. Grabowski 2001-03-20
6172383 Power MOSFET having voltage-clamped gate 2001-01-09
6159841 Method of fabricating lateral power MOSFET having metal strap layer to reduce distributed resistance Mohammad Kasem 2000-12-12
6140678 Trench-gated power MOSFET with protective diode Wayne B. Grabowski, Mohamed N. Darwish 2000-10-31
6096608 Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench 2000-08-01
6087862 Power MOSFET including internal power supply circuitry 2000-07-11