Issued Patents 2025
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12416093 | Electroless plating process | Chandrasekharan Nair, Darko Grujicic, Rengarajan Shanmugam, Srinivasan Raman, Roy Dittler +3 more | 2025-09-16 |
| 12341117 | Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates | Kyle McElhinny, Hongxia Feng, Xiaoying Guo, Steve Cho, Jung Kyu Han +4 more | 2025-06-24 |
| 12327773 | Package with underfill containment barrier | Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun Kane Jen, Vipul V. Mehta +4 more | 2025-06-10 |
| 12308329 | Chiplet first architecture for die tiling applications | Srinivas V. Pietambaram, Gang Duan, Deepak Kulkarni, Xiaoying Guo | 2025-05-20 |
| 12300620 | Inorganic-based embedded-die layers for modular semiconductive devices | Srinivas V. Pietambaram, Tarek A. Ibrahim, Kristof Darmawikarta, Debendra Mallik, Robert L. Sankman | 2025-05-13 |
| 12243825 | Hybrid conductive vias for electronic substrates | Srinivas V. Pietambaram | 2025-03-04 |
| 12218040 | Nested interposer with through-silicon via bridge die | Srinivas V. Pietambaram, Debendra Mallik, Kristof Darmawikarta, Ravindranath V. Mahajan | 2025-02-04 |