Issued Patents 2025
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414339 | Formation of gate spacers for strained PMOS gate-all-around transistor structures | Ashish Agrawal, Gilbert Dewey, Siddharth Chouksey, Jack T. Kavalieros | 2025-09-09 |
| 12388011 | Top gate recessed channel CMOS thin film transistor and methods of fabrication | Gilbert Dewey, Ryan Keech, Cory Bomberger, Ashish Agrawal, Willy Rachmady +1 more | 2025-08-12 |
| 12369399 | Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure | Willy Rachmady, Sudipto Naskar, Gilbert Dewey, Marko Radosavljevic, Nicole K. Thomas +2 more | 2025-07-22 |
| 12342614 | Asymmetric gate structures and contacts for stacked transistors | Patrick Morrow, Arunshankar Venkataraman, Sean T. Ma, Willy Rachmady, Nicole K. Thomas +2 more | 2025-06-24 |
| 12288803 | Transistor with isolation below source and drain | Willy Rachmady, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy +3 more | 2025-04-29 |
| 12255137 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more | 2025-03-18 |
| 12243875 | Forksheet transistors with dielectric or conductive spine | Seung Hoon Sung, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose, Varun MISHRA +4 more | 2025-03-04 |
| 12230635 | Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach | Nicole K. Thomas, Ehren Mannebach, Marko Radosavljevic | 2025-02-18 |
| 12224202 | Forming an oxide volume within a fin | Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more | 2025-02-11 |