Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170238 | Semiconductor die package with multi-lid structures and method for forming the same | Shu-Shen Yeh, Chia-Kuei Hsu, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng | 2024-12-17 |
| 12148684 | Package structure and method | Shu-Shen Yeh, Chin-Hua Wang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng | 2024-11-19 |
| 12125822 | Method of manufacturing a semiconductor device package having dummy dies | Shu-Shen Yeh, Po-Chen Lai, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng | 2024-10-22 |
| 12100664 | Semiconductor device with curved conductive lines and method of forming the same | Chia-Kuei Hsu, Ming-Chih Yew, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng | 2024-09-24 |
| 12094828 | Eccentric via structures for stress reduction | Shu-Shen Yeh, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin | 2024-09-17 |
| 12033913 | Chip package structure with lid and method for forming the same | Shu-Shen Yeh, Yu-Sheng Lin, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng | 2024-07-09 |
| 12033906 | Semiconductor package and manufacturing method thereof | Shu-Shen Yeh, Chin-Hua Wang, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng | 2024-07-09 |
| 11990418 | Chip package structure with buffer structure and method for forming the same | Chin-Hua Wang, Po-Chen Lai, Ping-Tai CHEN, Yu-Sheng Lin, Po-Yao Lin +1 more | 2024-05-21 |
| 11978722 | Structure and formation method of package containing chip structure with inclined sidewalls | Shu-Shen Yeh, Po-Chen Lai, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng | 2024-05-07 |