CW

Charles H. Wallace

IN Intel: 11 patents #119 of 4,430Top 3%
Overall (2024): #8,167 of 561,600Top 2%
11
Patents 2024

Issued Patents 2024

Patent #TitleCo-InventorsDate
12154855 Self-aligned patterning with colored blocking and structures resulting therefrom Mohit K. HARAN, Reken Patel, Richard E. Schenker 2024-11-26
12131991 Self aligned gratings for tight pitch interconnects and methods of fabrication Manish Chandhok, Leonard P. GULER, Paul A. Nyhus, Gobind Bisht, Jonathan Laib +5 more 2024-10-29
12131989 Vertical metal splitting using helmets and wrap-around dielectric spacers Leonard P. GULER, Paul A. Nyhus 2024-10-29
12107044 Metal oxycarbide resists as leave behind plugs Marie Krysak, Kevin Lin, Robert L. Bristol 2024-10-01
12087594 Colored gratings in microelectronic structures Gurpreet Singh, Eungnak Han, Manish Chandhok, Richard E. Schenker, Florian Gstrein +1 more 2024-09-10
12080639 Contact over active gate structures with metal oxide layers to inhibit shorting Rami Hourani, Manish Chandhok, Richard E. Schenker, Florian Gstrein, Leonard P. GULER +4 more 2024-09-03
12068314 Fabrication of gate-all-around integrated circuit structures having adjacent island structures Leonard P. GULER, William Hsu, Biswajeet Guha, Martin Weiss, Apratim Dhar +7 more 2024-08-20
12051623 Enhanced grating aligned patterning for EUV direct print processes Seyedhamed M Barghi, Shyam Benegal KADALI, Marvin Young Paik, Sheng-Po Fang, Leonard P. GULER +1 more 2024-07-30
12033894 Gate aligned contact and method to fabricate same Oleg Golonzka, Swaminathan Sivakumar, Tahir Ghani 2024-07-09
12002678 Gate spacing in integrated circuit structures Mohit K. HARAN, Paul A. Nyhus, Gurpreet Singh, Eungnak Han, David Shykind +1 more 2024-06-04
11972979 1D vertical edge blocking (VEB) via and plug Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Curtis W. Ward, Richard E. Schenker +4 more 2024-04-30