Issued Patents 2024
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183826 | Vertical field effect transistor with low-resistance bottom source-drain contact | Choonghyun Lee, Soon-Cheon Seo, Injo Ok | 2024-12-31 |
| 12176434 | Strained semiconductor FET devices with epitaxial quality improvement | Heng Wu, Ruilong Xie, Lan Yu | 2024-12-24 |
| 12154899 | Darlington pair bipolar junction transistor sensor | Bahman Hekmatshoartabari, Tak H. Ning | 2024-11-26 |
| 12156395 | Metal gate patterning for logic and SRAM in nanosheet devices | Choonghyun Lee, Takashi Ando, Jingyun Zhang | 2024-11-26 |
| 12155967 | Contextual positioning in virtual space | Martin G. Keen, Jeremy R. Fox, Bahman Hekmatshoartabari | 2024-11-26 |
| 12154985 | Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices | Ruilong Xie, Chen Zhang, Julien Frougier, Shogo Mochizuki | 2024-11-26 |
| 12144270 | Back end of line embedded RRAM structure with grain growth enhancement | Oleg Gluschenkov, Injo Ok, Soon-Cheon Seo | 2024-11-12 |
| 12144271 | Back end of line embedded RRAM structure with low forming voltage | Oleg Gluschenkov, Youngseok Kim, Injo Ok, Soon-Cheon Seo | 2024-11-12 |
| 12142526 | Stacked device with buried interconnect | Ruilong Xie, Chen Zhang, Heng Wu, Julien Frougier | 2024-11-12 |
| 12136671 | Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion | Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi | 2024-11-05 |
| 12127482 | Multi-state SOT-MRAM structure | Heng Wu, Bahman Hekmatshoartabari, Jingyun Zhang | 2024-10-22 |
| 12118662 | Optimizing computer-based generation of three-dimensional virtual objects | Jeremy R. Fox, Martin G. Keen, Bahman Hekmatshoartabari | 2024-10-15 |
| 12108686 | Paramagnetic hexagonal metal phase coupling spacer | Matthias Georg Gottwald, Stephen L. Brown | 2024-10-01 |
| 12100744 | Wrap around contact process margin improvement with early contact cut | Ruilong Xie, Veeraraghavan S. Basker, Andrew M. Greene, Yao Yao | 2024-09-24 |
| 12100766 | Integrated short channel omega gate FinFET and long channel FinFET | Oleg Gluschenkov, Ruilong Xie | 2024-09-24 |
| 12100653 | Resistance tunable fuse structure formed by embedded thin metal layers | Chih-Chao Yang, Miaomiao Wang, Donald F. Canaperi | 2024-09-24 |
| 12080640 | Self-aligned via to metal line for interconnect | Tao Li, Ruilong Xie, Tsung-Sheng Kang | 2024-09-03 |
| 12080714 | Buried local interconnect between complementary field-effect transistor cells | Ruilong Xie, Reinaldo Vega, Kangguo Cheng | 2024-09-03 |
| 12075627 | AI accelerator with MRAM, PCM, and recessed PCM bottom electrode | Ruilong Xie, Wei Wang, Tao Li, Tsung-Sheng Kang | 2024-08-27 |
| 12026605 | FeFET unit cells for neuromorphic computing | Nanbo Gong, Takashi Ando, Bahman Hekmatshoartabari | 2024-07-02 |
| 12016251 | Spin-orbit torque and spin-transfer torque magnetoresistive random-access memory stack | Heng Wu, Bahman Hekmatshoartabari, Ruilong Xie | 2024-06-18 |
| 12009435 | Integrated nanosheet field effect transistors and floating gate memory cells | Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker | 2024-06-11 |
| 12009422 | Self aligned top contact for vertical transistor | Choonghyun Lee, Christopher J. Waskiewicz, Chanro Park | 2024-06-11 |
| 12009395 | Self-aligned block for vertical FETs | Ruilong Xie, Junli Wang, Choonghyun Lee | 2024-06-11 |
| 11990412 | Buried power rails located in a base layer including first, second, and third etch stop layers | Ruilong Xie, Stuart A. Sieg, Somnath Ghosh, Kisik Choi, Rishikesh Krishnan | 2024-05-21 |