| 11855627 |
Asynchronous consensus circuit using multi-function threshold gate with input based adaptive threshold |
Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2023-12-26 |
|
| 11853666 |
Computer-aided design tool for wide-input logic initialization |
Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania |
2023-12-26 |
|
| 11855626 |
Asynchronous consensus circuit with stacked linear or paraelectric non-planar capacitors |
Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2023-12-26 |
|
| 11854593 |
Ferroelectric memory device integrated with a transition electrode |
Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2023-12-26 |
|
| 11844223 |
Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging |
Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni |
2023-12-12 |
|
| 11844225 |
Dual hydrogen barrier layer for memory devices integrated with low density film for logic structures and methods of fabrication |
Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more |
2023-12-12 |
|
| 11841757 |
Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic |
Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni |
2023-12-12 |
|
| 11844203 |
Conductive and insulative hydrogen barrier layer for memory devices |
Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more |
2023-12-12 |
|
| 11837268 |
Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset |
Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni |
2023-12-05 |
|
| 11839070 |
High density dual encapsulation materials for capacitors and methods of fabrication |
Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more |
2023-12-05 |
|
| 11836102 |
Low latency and high bandwidth artificial intelligence processor |
Rajeev Kumar Dokania, Ananda Samajdar, Sasikanth Manipatruni |
2023-12-05 |
|
| 11839088 |
Integrated via and bridge electrodes for memory array applications and methods of fabrication |
Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more |
2023-12-05 |
|
| 11832451 |
High density ferroelectric random access memory (FeRAM) devices and methods of fabrication |
Debraj Guhabiswas, Maria Isabel Perez, Jason Y. Wu, James David Clarkson, Gabriel Antonio Paulius Velarde +4 more |
2023-11-28 |
|
| 11829699 |
Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging |
Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni |
2023-11-28 |
|
| 11823725 |
Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling |
Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania |
2023-11-21 |
|
| 11816408 |
Computer-aided design tool for majority or minority inverter graph synthesis |
Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania |
2023-11-14 |
|
| 11817140 |
Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell |
Rajeev Kumar Dokania, Sasikanth Manipatruni |
2023-11-14 |
|
| 11817859 |
Asynchronous circuit with multi-input threshold gate logic and 1-input threshold gate |
Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania |
2023-11-14 |
|
| 11818897 |
Method of forming a stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell |
Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni |
2023-11-14 |
|
| 11809801 |
Computer-aided design tool for circuit logic initialization |
Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania |
2023-11-07 |
|
| 11810608 |
Manganese or scandium doped multi-element non-linear polar material gain memory bit-cell |
Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more |
2023-11-07 |
|
| 11800722 |
Common mode compensation for non-linear polar material based differential memory bit-cell having one transistor and multiple capacitors |
Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni |
2023-10-24 |
|
| 11791233 |
Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging |
Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni |
2023-10-17 |
|
| 11792997 |
Common mode compensation for differential multi-element non-linear polar material based gain memory bit-cell |
Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Sasikanth Manipatruni |
2023-10-17 |
|
| 11792998 |
Process integration flow for embedded memory with multi-pocket masks for decoupling processing of memory areas from non-memory areas |
Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2023-10-17 |
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