Issued Patents 2022
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11538754 | Random cut patterning | Shih-Wei Peng, Wei-Cheng Lin, Chih-Ming Lai | 2022-12-27 |
| 11532751 | Metal rail conductors for non-planar semiconductor devices | Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Kam-Tou Sio, Shih-Wei Peng +2 more | 2022-12-20 |
| 11532553 | Middle-end-of-line strap for standard cell | Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Kam-Tou Sio, Wei-Cheng Lin | 2022-12-20 |
| 11532482 | High-density semiconductor device | Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng +6 more | 2022-12-20 |
| 11515197 | Semiconductor device and method of forming the semiconductor device | Shih-Wei Peng, Wei-Cheng Lin | 2022-11-29 |
| 11515308 | Integrated circuit structure with hybrid cell design | Kam-Tou Sio | 2022-11-29 |
| 11495687 | Metal rail conductors for non-planar semiconductor devices | Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Kuo-Cheng Chiang +5 more | 2022-11-08 |
| 11482473 | Semiconductor device, and associated method and system | Shih-Wei Peng, Chia-Tien Wu | 2022-10-25 |
| 11476250 | Double rule integrated circuit layouts for a dual transmission gate | Shih-Wei Peng, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin | 2022-10-18 |
| 11444073 | Power distribution network | Kam-Tou Sio, Wei-Cheng Lin | 2022-09-13 |
| 11429774 | Variable width nano-sheet field-effect transistor cell structure | Wei-An Lai, Wei-Cheng Lin, Yan-Hao Chen, Lipen Yuan, Hui-Zhong Zhuang +1 more | 2022-08-30 |
| 11424154 | Buried metal for FinFET device and method | Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young | 2022-08-23 |
| 11409937 | Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same | Wei-Cheng Lin, Hui-Ting Yang, Lipen Yuan, Wei-An Lai | 2022-08-09 |
| 11374005 | Semiconductor structure and method of forming the same | Shih-Wei Peng, Te-Hsin Chiu, Wei-Cheng Lin | 2022-06-28 |
| 11355487 | Layout designs of integrated circuits having backside routing tracks | Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin | 2022-06-07 |
| 11328957 | Semiconductor device and manufacturing method thereof | Shih-Wei Peng, Wei-Cheng Lin | 2022-05-10 |
| 11309311 | Methods of resistance and capacitance reduction to circuit output nodes | Po-Chia Lai, Shang-Wei Fang, Meng-Hung Shen, Ting-Wei Chiang, Jung-Chan Yang +1 more | 2022-04-19 |
| 11309247 | Semiconductor device, and associated method and system | Shih-Wei Peng, Wei-Cheng Lin | 2022-04-19 |
| 11302631 | Integrated circuit cells and related methods | Te-Hsin Chiu, Shih-Wei Peng | 2022-04-12 |
| 11296070 | Integrated circuit with backside power rail and backside interconnect | Shih-Wei Peng, Guo-Huei Wu | 2022-04-05 |
| 11282829 | Integrated circuit with mixed row heights | Kam-Tou Sio, Chung-Hsing Wang, Yi-Kan Cheng | 2022-03-22 |
| 11270936 | Integrated circuit including supervia and method of making | Kam-Tou Sio, Wei-Cheng Lin | 2022-03-08 |
| 11257670 | Method of manufacturing a semiconductor device, and associated semiconductor device and system | Shih-Wei Peng, Chia-Tien Wu | 2022-02-22 |
| 11232248 | Routing-resource-improving method of generating layout diagram and system for same | Shih-Wei Peng, Wei-Cheng Lin, Jay Yang | 2022-01-25 |
| 11222157 | Pin access hybrid cell height design | Kam-Tou Sio | 2022-01-11 |