Issued Patents 2022
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532562 | Routing structure and method of forming the same | Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang | 2022-12-20 |
| 11501052 | Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing | Sheng-Hsiung Chen, Huang-Yu Chen, Jerry Chang Jui Kao | 2022-11-15 |
| 11437319 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang +6 more | 2022-09-06 |
| 11366951 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Kuo-Nan Yang | 2022-06-21 |
| 11347922 | Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang | 2022-05-31 |
| 11282829 | Integrated circuit with mixed row heights | Kam-Tou Sio, Jiann-Tyng Tzeng, Yi-Kan Cheng | 2022-03-22 |
| 11251124 | Power grid structures and method of forming the same | Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Stefan Rusu, Chin-Shen Lin | 2022-02-15 |
| 11239154 | Fishbone structure enhancing spacing with adjacent conductive line in power network | Chien-Ju Chao, Fang-Yu Fan, Yi-Chuin Tsai, Kuo-Nan Yang | 2022-02-01 |
| 11227093 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Hiranmay Biswas | 2022-01-18 |