Issued Patents 2022
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532586 | Connecting techniques for stacked substrates | Hsiang-Jen Tseng, Wei-Yu Chen, Ting-Wei Chiang | 2022-12-20 |
| RE49331 | Masks formed based on integrated circuit layout design having cell that includes extended active region | Lee-Chung Lu, Hui-Zhong Zhuang, Chang-Yu Wu | 2022-12-13 |
| 11508659 | Interconnect structure in semiconductor device and method of forming the same | Guo-Huei Wu, Shun Li Chen, Hui-Zhong Zhuang, Chih-Liang Chen | 2022-11-22 |
| 11476250 | Double rule integrated circuit layouts for a dual transmission gate | Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Pin-Dai Sue, Wei-Cheng Lin | 2022-10-18 |
| 11469221 | Integrated circuit and manufacturing method thereof | Xin-Yong WANG, Chih-Liang Chen | 2022-10-11 |
| 11461528 | Integrated circuit, system for and method of forming an integrated circuit | Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu +3 more | 2022-10-04 |
| 11444071 | Multi-bit structure | Shao-Lun Chien, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen | 2022-09-13 |
| 11437319 | Integrated circuit having a high cell density | Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-Yuan Chang, Lee-Chung Lu, Po-Hsiang Huang +6 more | 2022-09-06 |
| 11417601 | Semiconductor device and manufacturing method thereof | Xin-Yong WANG, Liu HAN, Chih-Liang Chen | 2022-08-16 |
| 11417588 | Semiconductor structure and layout method of a semiconductor structure | Wei-Ren Chen, Chih-Liang Chen, Wei Ling Chang, Hui-Zhong Zhuang | 2022-08-16 |
| 11409938 | Integrated circuit and method of manufacturing same | Ting-Wei Chiang, Hui-Zhong Zhuang | 2022-08-09 |
| 11374003 | Integrated circuit | Guo-Huei Wu, Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen | 2022-06-28 |
| 11362110 | Semiconductor structure and method for manufacturing the same | Pochun Wang, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen | 2022-06-14 |
| 11362090 | Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same | Guo-Huei Wu, Pochun Wang, Chih-Liang Chen | 2022-06-14 |
| 11355488 | Integrated circuit layout method, device, and system | Chien-Ying Chen, Lee-Chung Lu, Ta-Pen Guo | 2022-06-07 |
| 11315874 | Cell structure with intermediate metal layers for power supplies | Chih-Liang Chen, Hui-Zhong Zhuang, Shun Li Chen, Ting Yu Chen | 2022-04-26 |
| 11302787 | Integrated circuit layouts with source and drain contacts of different widths | Shang-Syuan Ciou, Hui-Zhong Zhuang, Jung-Chan Yang | 2022-04-12 |
| 11295055 | Transmission gate structure and method | Shao-Lun Chien, Pin-Dai Sue, Ting-Wei Chiang, Ting Yu Chen | 2022-04-05 |
| 11275885 | Engineering change order cell structure having always-on transistor | Shun Li Chen, Ting Yu Chen, Wei Ling Chang | 2022-03-15 |
| 11239228 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2022-02-01 |
| 11217553 | Connection structure for stacked substrates | Hsiang-Jen Tseng, Wei-Yu Chen, Ting-Wei Chiang | 2022-01-04 |
| 11216608 | Reduced area standard cell abutment configurations | Chi-Yu Lu, Hui-Zhong Zhuang, Pin-Dai Sue, Yi-Hsin Ko | 2022-01-04 |