Issued Patents 2020
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10871518 | Systems and methods for determining systematic defects | Sandeep Kumar Goel, Ankita Patidar | 2020-12-22 |
| 10867098 | System and method for ESL modeling of machine learning | Kai-Yuan Ting, Sandeep Kumar Goel, Tze-Chiang Huang | 2020-12-15 |
| 10867089 | Electrical system level (ESL) battery discharge simulation | Charlie Zhou, Kai-Yuan Ting, Sandeep Kumar Goel, Tze-Chiang Huang | 2020-12-15 |
| 10790197 | Semiconductor arrangement and formation thereof | I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang | 2020-09-29 |
| 10782318 | Test probing structure | Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh +2 more | 2020-09-22 |
| 10776538 | Function safety and fault management modeling at electrical system level (ESL) | Kai-Yuan Ting, Sandeep Kumar Goel, Mei Hsu Wong, Hsin-Cheng Chen | 2020-09-15 |
| 10748870 | Tri-layer COWOS structure | Chen-Hua Yu, Shang-Yun Hou | 2020-08-18 |
| 10719648 | System and method for system-level parameter estimation | Tze-Chiang Huang, Kai-Yuan Ting, Sandeep Kumar Goel, Shereef Shehata, Mei Hsu Wong | 2020-07-21 |
| 10692763 | Integrated antenna on interposer substrate | Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu | 2020-06-23 |
| 10685157 | Power-aware scan partitioning | Ankita Patidar, Sandeep Kumar Goel | 2020-06-16 |
| 10680627 | Phase-locked loop monitor circuit | Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yen-Hao Huang | 2020-06-09 |
| 10678973 | Machine-learning design enablement platform | Yi-Lin Chuang, Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou | 2020-06-09 |
| 10673603 | Integrated circuit with radio frequency interconnect | Huan-Neng Chen, William Wu Shen, Chewn-Pu Jou, Feng-Wei Kuo, Lan-Chou Cho +2 more | 2020-06-02 |
| 10666578 | Network-on-chip system and a method of generating the same | Ravi Venugopalan, Sandeep Kumar Goel | 2020-05-26 |
| 10539617 | Scan architecture for interconnect testing in 3D integrated circuits | Sandeep Kumar Goel, Saman M. I. Adham, Marat Gershoig | 2020-01-21 |