Issued Patents 2020
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741451 | FinFET having insulating layers between gate and source/drain contacts | Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie | 2020-08-11 |
| 10741656 | Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same | Ruilong Xie, Shesh Mani Pandey, Laertis Economikos | 2020-08-11 |
| 10734233 | FinFET with high-k spacer and self-aligned contact capping layer | Guowei Xu, Keith H. Tabakman | 2020-08-04 |
| 10727136 | Integrated gate contact and cross-coupling contact formation | Ruilong Xie, Chanro Park, Laertis Economikos | 2020-07-28 |
| 10727067 | Late gate cut using selective conductor deposition | David Paul Brunco | 2020-07-28 |
| 10714591 | Gate structure for a transistor device with a novel pillar structure positioned thereabove | Ruilong Xie, Youngtag Woo | 2020-07-14 |
| 10714577 | Etch stop layer for use in forming contacts that extend to multiple depths | Wei Hong, Hsien-Ching Lo | 2020-07-14 |
| 10707207 | Method, apparatus, and system for improved gate connections on isolation structures in FinFET devices | Dali Shao | 2020-07-07 |
| 10707303 | Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts | Haiting Wang, Zhenyu Hu | 2020-07-07 |
| 10707206 | Gate cut isolation formed as layer against sidewall of dummy gate mandrel | Laertis Economikos, Ruilong Xie | 2020-07-07 |
| 10699957 | Late gate cut using selective dielectric deposition | Ruilong Xie, Jiehui Shu, Chanro Park, Laertis Economikos | 2020-06-30 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven R. Soss, Lars Liebmann +1 more | 2020-06-30 |
| 10692812 | Interconnects with variable space mandrel cuts formed by block patterning | Ravi Prakash Srivastava, Jiehui Shu | 2020-06-23 |
| 10692987 | IC structure with air gap adjacent to gate structure and methods of forming same | Haiting Wang, Guowei Xu | 2020-06-23 |
| 10685840 | Gate structures | Jiehui Shu | 2020-06-16 |
| 10685881 | Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a semiconductor device | Guowei Xu, Haiting Wang | 2020-06-16 |
| 10685874 | Self-aligned cuts in an interconnect structure | Ruilong Xie, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche | 2020-06-16 |
| 10665590 | Wrap-around contact surrounding epitaxial regions of integrated circuit structures and method of forming same | Ruilong Xie, William J. Taylor, Jr. | 2020-05-26 |
| 10656970 | Scheduling graph computing on heterogeneous processing resources based on energy efficiency | Yinglong Xia | 2020-05-19 |
| 10651173 | Single diffusion cut for gate structures | Guowei Xu, Ruilong Xie, Haiting Wang | 2020-05-12 |
| 10651284 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann +3 more | 2020-05-12 |
| 10636893 | Replacement metal gate with reduced shorting and uniform chamfering | Guowei Xu | 2020-04-28 |
| 10636894 | Fin-type transistors with spacers on the gates | Yanping Shen, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi +4 more | 2020-04-28 |
| 10636890 | Chamfered replacement gate structures | Haiting Wang, Rongtao Lu, Chih-Chiang Chang, Guowei Xu, Scott Beasor +1 more | 2020-04-28 |
| 10629694 | Gate contact and cross-coupling contact formation | Ruilong Xie, Haiting Wang, Scott Beasor | 2020-04-21 |