Issued Patents 2019
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10490569 | Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings | Mitsuteru Mushiga, Hisakazu Otoi, Kensuke Yamaguchi, James Kai, Zhixin Cui +2 more | 2019-11-26 |
| 10490568 | Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof | James Kai, Murshed Chowdhury, Jin Liu | 2019-11-26 |
| 10431313 | Grouping memory cells into sub-blocks for program speed uniformity | Zhengyi Zhang, Yingda Dong, James Kai | 2019-10-01 |
| 10388666 | Concurrent formation of memory openings and contact openings for a three-dimensional memory device | James Kai, Zhixin Cui, Murshed Chowdhury, Tong Zhang | 2019-08-20 |
| 10373969 | Three-dimensional memory device including partially surrounding select gates and fringe field assisted programming thereof | Yanli Zhang, Peng Zhang, Yingda Dong | 2019-08-06 |
| 10354956 | Three-dimensional memory device containing hydrogen diffusion barrier structures for CMOS under array architecture and method of making the same | Jixin Yu, Daxin Mao, Hiroyuki Ogawa | 2019-07-16 |
| 10355007 | Three-dimensional memory structure having a back gate electrode | Xiying Costa, Dana Lee, Yanli Zhang, Yingda Dong, Akira Matsudaira | 2019-07-16 |
| 10355009 | Concurrent formation of memory openings and contact openings for a three-dimensional memory device | James Kai, Zhixin Cui, Murshed Chowdhury, Tong Zhang | 2019-07-16 |
| 10355015 | Three-dimensional NAND memory device with common bit line for multiple NAND strings in each memory block | Yanli Zhang, James Kai | 2019-07-16 |
| 10297610 | Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same | James Kai, Shinsuke Yada, Akihisa SAI, Sayako Nagamine, Takashi Orimoto +1 more | 2019-05-21 |
| 10290643 | Three-dimensional memory device containing floating gate select transistor | James Kai, Yanli Zhang, Peng Zhang | 2019-05-14 |
| 10269620 | Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof | Jixin Yu, Zhenyu Lu, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi +2 more | 2019-04-23 |
| 10256248 | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | Zhenyu Lu, Jixin Yu, Fumiaki Toyama, Yuki Mizutani, Hiroyuki Ogawa +5 more | 2019-04-09 |
| 10249640 | Within-array through-memory-level via structures and method of making thereof | Jixin Yu, Zhenyu Lu, Alexander Chu, Kensuke Yamaguchi, Hiroyuki Ogawa +2 more | 2019-04-02 |
| 10236300 | On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same | Yanli Zhang, Masanori Tsutsumi, Shinsuke Yada, Sayako Nagamine | 2019-03-19 |
| 10224407 | High voltage field effect transistor with laterally extended gate dielectric and method of making thereof | Murshed Chowdhury, Andrew Lin, James Kai, Yanli Zhang | 2019-03-05 |
| 10224104 | Three dimensional NAND memory device with common bit line for multiple NAND strings in each memory block | Murshed Chowdhury, Jin Liu, Yanli Zhang, Andrew Lin, Raghuveer S. Makala | 2019-03-05 |