Issued Patents 2019
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515897 | Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same | Masatoshi Nishikawa, Akio Nishida, Murshed Chowdhury, Takahito Fujita, Kiyokazu Shishido | 2019-12-24 |
| 10515907 | Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same | Takahito Fujita, Kiyokazu Shishido | 2019-12-24 |
| 10416820 | Display device | Jean Mugiraneza, Yasuhiro Sugita, Kazutoshi Kida, Tomohiro Kimura | 2019-09-17 |
| 10403632 | 3D NAND device with five-folded memory stack structure configuration | Hiroyuki Tanaka | 2019-09-03 |
| 10386964 | Display device fitted with position input function | Kazutoshi Kida, Kenshi Tada, Yasuhiro Sugita, Takenori Maruyama | 2019-08-20 |
| 10381371 | Through-memory-level via structures for a three-dimensional memory device | Fumiaki Toyama, Yuki Mizutani | 2019-08-13 |
| 10381443 | Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device | Kazuyo Matsumoto, Yasuo Kasagi, Satoshi Shimizu, Yohei Masamori, Jixin Yu +2 more | 2019-08-13 |
| 10355017 | CMOS devices containing asymmetric contact via structures and method of making the same | Hiroshi Nakatsuji, Kiyokazu Shishido | 2019-07-16 |
| 10354956 | Three-dimensional memory device containing hydrogen diffusion barrier structures for CMOS under array architecture and method of making the same | Jixin Yu, Daxin Mao, Johann Alsmeier | 2019-07-16 |
| 10290645 | Three-dimensional memory device containing hydrogen diffusion barrier layer for CMOS under array architecture and method of making thereof | Hiroshi Nakatsuji, Kazutaka Yoshizawa | 2019-05-14 |
| 10269620 | Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof | Jixin Yu, Zhenyu Lu, Daxin Mao, Kensuke Yamaguchi, Sung-Tae Lee +2 more | 2019-04-23 |
| 10269817 | Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof | James Kai | 2019-04-23 |
| 10256248 | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Yuki Mizutani +5 more | 2019-04-09 |
| 10256099 | Transistors having semiconductor-metal composite gate electrodes containing different thickness interfacial dielectrics and methods of making thereof | Jun Akaiwa, Kiyokazu Shishido | 2019-04-09 |
| 10249640 | Within-array through-memory-level via structures and method of making thereof | Jixin Yu, Zhenyu Lu, Alexander Chu, Kensuke Yamaguchi, Daxin Mao +2 more | 2019-04-02 |
| 10203808 | Position input device and display device having position input function | Takenori Maruyama, Kazutoshi Kida, Kenshi Tada, Shinji Yamagishi | 2019-02-12 |
| 10198126 | Position inputting device and display device with position inputting function | Takenori Maruyama, Kazutoshi Kida, Kenshi Tada | 2019-02-05 |
| 10192877 | Three-dimensional memory device with level-shifted staircase structures and method of making thereof | Naoto Norizuki, Yasuchika Okizumi, Shogo Mada | 2019-01-29 |
| 10175836 | Conductive sheet, touch panel device, and display device | Hiroki Makino, Mikihiro Noma, Tomotoshi Tsujioka, Daiji Kitagawa, Yasuhiro Sugita | 2019-01-08 |