Issued Patents 2019
Showing 76–100 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10283606 | Vertical fin with a gate structure having a modified gate geometry | Kangguo Cheng | 2019-05-07 |
| 10283592 | Approach to minimization of strain loss in strained fin field effect transistors | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2019-05-07 |
| 10269957 | Reduced resistance source and drain extensions in vertical field effect transistors | Chun Wing Yeung, Chen Zhang | 2019-04-23 |
| 10263075 | Nanosheet CMOS transistors | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2019-04-16 |
| 10263100 | Buffer regions for blocking unwanted diffusion in nanosheet transistors | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2019-04-16 |
| 10262890 | Method of forming silicon hardmask | Kangguo Cheng | 2019-04-16 |
| 10262861 | Forming a fin cut in a hardmask | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2019-04-16 |
| 10256154 | Uniform shallow trench isolation | Kangguo Cheng, Junli Wang, Chen Zhang | 2019-04-09 |
| 10249755 | Transistor with asymmetric source/drain overlap | Kangguo Cheng, Heng Wu, Zhenxing Bi | 2019-04-02 |
| 10249731 | Vertical FET with sharp junctions | Juntao Li, Kangguo Cheng, Heng Wu | 2019-04-02 |
| 10249541 | Forming a hybrid channel nanosheet semiconductor structure | Kangguo Cheng | 2019-04-02 |
| 10242983 | Semiconductor device with increased source/drain area | Kangguo Cheng, Chi-Chun Liu, Jie Yang | 2019-03-26 |
| 10243061 | Nanosheet transistor | Kangguo Cheng, Juntao Li, Heng Wu | 2019-03-26 |
| 10242881 | Self-aligned single dummy fin cut with tight pitch | Kangguo Cheng, Cheng Chi, Chi-Chun Liu | 2019-03-26 |
| 10236346 | Transistor having a high germanium percentage fin channel and a gradient source/drain junction doping profile | Zhenxing Bi, Kangguo Cheng, Chen Zhang | 2019-03-19 |
| 10236364 | Tunnel transistor | Kangguo Cheng, Heng Wu, Zhenxing Bi | 2019-03-19 |
| 10236290 | Method and structure for improving vertical transistor | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2019-03-19 |
| 10229985 | Vertical field-effect transistor with uniform bottom spacer | Juntao Li, Kangguo Cheng, Heng Wu | 2019-03-12 |
| 10229983 | Methods and structures for forming field-effect transistors (FETs) with low-k spacers | Huiming Bu, Kangguo Cheng | 2019-03-12 |
| 10224431 | Wrapped source/drain contacts with enhanced area | Kangguo Cheng, Zuoguang Liu, Heng Wu | 2019-03-05 |
| 10224246 | Multi-layer filled gate cut to prevent power rail shorting to gate structure | Kangguo Cheng, Hao Tang | 2019-03-05 |
| 10217841 | Forming an uniform L-shaped inner spacer for a vertical transport fin field effect transistor (VT FinFET) | Kangguo Cheng, Juntao Li, Jingyun Zhang | 2019-02-26 |
| 10217867 | Uniform fin dimensions using fin cut hardmask | Kangguo Cheng | 2019-02-26 |
| 10217707 | Trench contact resistance reduction | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2019-02-26 |
| 10211302 | Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts | Kangguo Cheng | 2019-02-19 |