Issued Patents 2019
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10304747 | Dual liner silicide | Balasubramanian Pranatharthiharan, Ruilong Xie | 2019-05-28 |
| 10297452 | Methods of forming a gate contact structure for a transistor | Ruilong Xie, Hui Zang, Kangguo Cheng, Tenko Yamashita | 2019-05-21 |
| 10290636 | Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods | Qing Liu, Ruilong Xie, Xiuyu Cai | 2019-05-14 |
| 10283423 | Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions | Tenko Yamashita, Hui Zang | 2019-05-07 |
| 10276659 | Air gap adjacent a bottom source/drain region of vertical transistor device | Ruilong Xie, Kangguo Cheng, Tenko Yamashita | 2019-04-30 |
| 10276573 | FinFET including tunable fin height and tunable fin width ratio | Xiuyu Cai, Qing Liu, Ruilong Xie | 2019-04-30 |
| 10269920 | Nanosheet transistors having thin and thick gate dielectric material | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2019-04-23 |
| 10269983 | Stacked nanosheet field-effect transistor with air gap spacers | Julien Frougier, Ruilong Xie, Hui Zang, Kangguo Cheng, Tenko Yamashita | 2019-04-23 |
| 10256304 | High doped III-V source/drain junctions for field effect transistors | Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie | 2019-04-09 |
| 10256231 | Forming vertical transistors and metal-insulator-metal capacitors on the same chip | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2019-04-09 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Yi Qi, Hsien-Ching Lo, Jianwei Peng, Wei Hong, Yanping Shen +5 more | 2019-04-02 |
| 10249758 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui | 2019-04-02 |
| 10249736 | Aspect ratio trapping in channel last process | Effendi Leobandung | 2019-04-02 |
| 10249714 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | Dechao Guo, Shogo Mochizuki, Andreas Scholze | 2019-04-02 |
| 10249502 | Low resistance source drain contact formation with trench metastable alloys and laser annealing | Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita | 2019-04-02 |
| 10242916 | Stress memorization technique for strain coupling enhancement in bulk FINFET device | Kangguo Cheng, Juntao Li | 2019-03-26 |
| 10243074 | Vertical vacuum channel transistor | Qing Liu, Ruilong Xie | 2019-03-26 |
| 10242991 | Highly compact floating gate analog memory | Effendi Leobandung, Yulong Li, Paul M. Solomon | 2019-03-26 |
| 10236363 | Vertical field-effect transistors with controlled dimensions | Ruilong Xie, Kangguo Cheng, Tenko Yamashita | 2019-03-19 |
| 10224420 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2019-03-05 |
| 10224417 | Fin field effect transistor fabrication and devices having inverted T-shaped gate | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2019-03-05 |
| 10217672 | Vertical transistor devices with different effective gate lengths | Ruilong Xie, Tenko Yamashita, Kangguo Cheng | 2019-02-26 |
| 10204907 | Metal-insulator-metal capacitor analog memory unit cell | Effendi Leobandung, Yulong Li, Paul M. Solomon | 2019-02-12 |
| 10199480 | Controlling self-aligned gate length in vertical transistor replacement gate flow | Ruilong Xie, Tenko Yamashita, Kangguo Cheng | 2019-02-05 |
| 10199464 | Techniques for VFET top source/drain epitaxy | Kangguo Cheng, Cheng Chi, Chi-Chun Liu, Ruilong Xie, Tenko Yamashita | 2019-02-05 |