Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10431565 | Wafer edge partial die engineered for stacked die yield | Myongseob Kim, Cheang-Whang Chang | 2019-10-01 |
| 10319606 | Chip package assembly with enhanced interconnects and method for fabricating the same | Jaspreet S. Gandhi, Tien-Yu Lee, Ivor G. Barber, Suresh Ramalingam | 2019-06-11 |
| 10262911 | Circuit for and method of testing bond connections between a first die and a second die | Yuqing Gong, Myongseob Kim, Suresh Parameswaran, Cheang-Whang Chang, Boon Yong Ang | 2019-04-16 |