Issued Patents 2018
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141320 | Multiple-bit electrical fuses | Kangguo Cheng | 2018-11-27 |
| 10084067 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2018-09-25 |
| 10062615 | Stacked nanowire devices | Kangguo Cheng, Juntao Li | 2018-08-28 |
| 10002876 | FinFET vertical flash memory | Arvind Kumar, Carl Radens | 2018-06-19 |
| 9997606 | Fully depleted SOI device for reducing parasitic back gate capacitance | Kangguo Cheng | 2018-06-12 |
| 9997618 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Juntao Li, Xin Miao | 2018-06-12 |
| 9966253 | Forming nanotips | Kangguo Cheng, Juntao Li, Shogo Mochizuki | 2018-05-08 |
| 9960168 | Capacitor strap connection structure and fabrication method | Veeraraghavan S. Basker, Kangguo Cheng, Benjamin Cipriany, Brian J. Greene, Ali Khakifirooz +2 more | 2018-05-01 |
| 9954109 | Vertical transistor including controlled gate length and a self-aligned junction | Kangguo Cheng | 2018-04-24 |
| 9929060 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2018-03-27 |
| 9917199 | Method for reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions | Kangguo Cheng | 2018-03-13 |
| 9917021 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2018-03-13 |
| 9911834 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Juntao Li, Xin Miao | 2018-03-06 |
| 9865509 | FinFET CMOS with Si NFET and SiGe PFET | Kangguo Cheng, Jeehwan Kim | 2018-01-09 |