Issued Patents 2017
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9817029 | Test probing structure | Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2017-11-14 |
| 9754847 | Circuit probing structures and methods for probing the same | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2017-09-05 |
| 9704766 | Interposers of 3-dimensional integrated circuit package systems and methods of designing the same | Sandeep Kumar Goel, Chung-Sheng Yuan, Tom C. Chen, Chao-Yang Yeh, Chin-Chou Liu +1 more | 2017-07-11 |
| 9671457 | 3D IC testing apparatus | Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen | 2017-06-06 |
| 9664707 | Testing holders for chip unit and die package | Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2017-05-30 |
| 9658281 | Alignment testing for tiered semiconductor structure | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee | 2017-05-23 |
| 9640447 | Test circuit and method | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang | 2017-05-02 |
| 9606155 | Capacitance measurement circuit and method | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang | 2017-03-28 |
| 9568543 | Structure and method for testing stacked CMOS structure | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2017-02-14 |