Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9817029 | Test probing structure | Mill-Jer Wang, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2017-11-14 |
| 9689914 | Method of testing a three-dimensional integrated circuit | Hsiang-Tai Lu, Chih-Hsien Lin | 2017-06-27 |
| 9679840 | Method for layout design and structure with inter-layer vias | Yi-Lin Chuang, Jia-Jye Shen | 2017-06-13 |
| 9613174 | Common template for electronic article | William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Sean Lee, Chung-Sheng Yuan +2 more | 2017-04-04 |