Issued Patents 2017
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9679840 | Method for layout design and structure with inter-layer vias | Ching-Fang Chen, Jia-Jye Shen | 2017-06-13 |
| 9601478 | Oxide definition (OD) gradient reduced semiconductor device | Chun-Cheng Ku, Chin-Her Chien, Wei-Pin Changchien | 2017-03-21 |