Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812449 | Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance | Borna J. Obradovic, Mark S. Rodder, Wei-E Wang | 2017-11-07 |
| 9805795 | Zero leakage, high noise margin coupled giant spin hall based retention latch | Borna J. Obradovic | 2017-10-31 |
| 9806193 | Stress in trigate devices using complimentary gate fill materials | Martin D. Giles, Ravi Pillarisetty, Jack T. Kavalieros | 2017-10-31 |
| 9793403 | Multi-layer fin field effect transistor devices and methods of forming the same | Borna J. Obradovic, Robert C. Bowen, Wei-E Wang, Mark S. Rodder | 2017-10-17 |
| 9773904 | Vertical field effect transistor with biaxial stressor layer | Borna J. Obradovic, Chris Bowen, Palle Dharmendar, Mark S. Rodder | 2017-09-26 |
| 9685564 | Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures | Rwik Sengupta, Mark S. Rodder, Joon Goo Hong | 2017-06-20 |
| 9614002 | 0T bi-directional memory cell | Ryan M. Hatcher, Borna J. Obradovic, Jorge A. Kittl, Joon Goo Hong | 2017-04-04 |
| 9595581 | Silicon and silicon germanium nanowire structures | Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles +3 more | 2017-03-14 |