MR

Mark S. Rodder

Samsung: 23 patents #47 of 15,326Top 1%
Overall (2017): #1,124 of 506,227Top 1%
23
Patents 2017

Issued Patents 2017

Patent #TitleCo-InventorsDate
9853114 Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same Borna J. Obradovic 2017-12-26
9831323 Structure and method to achieve compressively strained Si NS Jorge A. Kittl, Ganesh Hegde, Robert C. Bowen, Borna J. Obradovic 2017-11-28
9812449 Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance Borna J. Obradovic, Titash Rakshit, Wei-E Wang 2017-11-07
9793403 Multi-layer fin field effect transistor devices and methods of forming the same Borna J. Obradovic, Robert C. Bowen, Titash Rakshit, Wei-E Wang 2017-10-17
9773886 Nanosheet and nanowire devices having doped internal spacers and methods of manufacturing the same Dharmendar Reddy Palle, Jorge A. Kittl 2017-09-26
9773906 Relaxed semiconductor layers with reduced defects and methods of forming the same Wei-E Wang, Ganesh Hedge, Christopher Rhys Bowen 2017-09-26
9773904 Vertical field effect transistor with biaxial stressor layer Borna J. Obradovic, Chris Bowen, Titash Rakshit, Palle Dharmendar 2017-09-26
9768062 Method for forming low parasitic capacitance source and drain contacts Jorge A. Kittl, David Seo, Kota OIKAWA, Kim Changhwa, Rwik Sengupta 2017-09-19
9728502 Metal oxysilicate diffusion barriers for damascene metallization with low RC delays and methods for forming the same Ganesh Hegde, Rwik Sengupta, Chris Bowen 2017-08-08
9716176 FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same Borna J. Obradovic, Robert C. Bowen 2017-07-25
9711414 Strained stacked nanosheet FETS and/or quantum well stacked nanosheet Ryan M. Hatcher, Robert C. Bowen, Borna J. Obradovic, Joon Goo Hong 2017-07-18
9698234 Interface layer for gate stack using O3 post treatment Jorge A. Kittl, Wei-E Wang 2017-07-04
9691860 Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators Wei-E Wang, Rwik Sengupta 2017-06-27
9685564 Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures Rwik Sengupta, Joon Goo Hong, Titash Rakshit 2017-06-20
9685509 Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions Jorge A. Kittl, Robert C. Bowen 2017-06-20
9653287 S/D connection to individual channel layers in a nanosheet FET Joon Goo Hong, Jorge A. Kittl, Borna J. Obradovic 2017-05-16
9647098 Thermionically-overdriven tunnel FETs and methods of fabricating the same Borna J. Obradovic, Robert C. Bowen, Dharmendar Reddy Palle 2017-05-09
9634140 Fabricating metal source-drain stressor in a MOS device channel Jorge A. Kittl, Ganesh Hegde 2017-04-25
9613907 Low resistivity damascene interconnect Ganesh Hegde, Jorge A. Kittl, Robert C. Bowen 2017-04-04
9601586 Methods of forming semiconductor devices, including forming a metal layer on source/drain regions Jorge A. Kittl, Joon Goo Hong 2017-03-21
9583590 Integrated circuit devices including FinFETs and methods of forming the same Borna J. Obradovic, Robert C. Bowen 2017-02-28
9570609 Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same Borna J. Obradovic, Robert C. Bowen 2017-02-14
9570395 Semiconductor device having buried power rail Rwik Sengupta, Joon Goo Hong 2017-02-14