Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812449 | Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance | Borna J. Obradovic, Titash Rakshit, Mark S. Rodder | 2017-11-07 |
| 9793403 | Multi-layer fin field effect transistor devices and methods of forming the same | Borna J. Obradovic, Robert C. Bowen, Titash Rakshit, Mark S. Rodder | 2017-10-17 |
| 9773906 | Relaxed semiconductor layers with reduced defects and methods of forming the same | Mark S. Rodder, Ganesh Hedge, Christopher Rhys Bowen | 2017-09-26 |
| 9698234 | Interface layer for gate stack using O3 post treatment | Jorge A. Kittl, Mark S. Rodder | 2017-07-04 |
| 9691860 | Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators | Mark S. Rodder, Rwik Sengupta | 2017-06-27 |