Issued Patents 2017
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9842933 | Formation of bottom junction in vertical FET devices | Hiroaki Niimi, Kwan-Yong Lim, Daniel Chanemougame | 2017-12-12 |
| 9825032 | Metal layer routing level for vertical FET SRAM and logic cell scaling | Bipul C. Paul | 2017-11-21 |
| 9805988 | Method of forming semiconductor structure including suspended semiconductor layer and resulting structure | Guillaume Bouche | 2017-10-31 |
| 9799751 | Methods of forming a gate structure on a vertical transistor device | John H. Zhang, Kwan-Yong Lim | 2017-10-24 |
| 9773708 | Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI | John H. Zhang, Kwan-Yong Lim | 2017-09-26 |
| 9748335 | Method, apparatus and system for improved nanowire/nanosheet spacers | Deepak Nayak | 2017-08-29 |
| 9698025 | Directed self-assembly material growth mask for forming vertical nanowires | Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob | 2017-07-04 |
| 9647086 | Early PTS with buffer for channel doping control | Jody A. Fronheiser, Xin Miao, Joseph S. Washington, Pierre Morin | 2017-05-09 |
| 9640636 | Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device | John H. Zhang, Kwan-Yong Lim, Hiroaki Niimi | 2017-05-02 |
| 9613817 | Method of enhancing surface doping concentration of source/drain regions | Vimal Kamineni | 2017-04-04 |
| 9577042 | Semiconductor structure with multilayer III-V heterostructures | Rohit Galatage | 2017-02-21 |
| 9570588 | Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material | Murat Kerem Akarvardar | 2017-02-14 |
| 9564486 | Self-aligned dual-height isolation for bulk FinFET | Murat Kerem Akarvardar, Kangguo Cheng, Bruce B. Doris, Jody A. Fronheiser, Ajey Poovannummoottil Jacob +2 more | 2017-02-07 |
| 9543215 | Punch-through-stop after partial fin etch | Kwan-Yong Lim, Chanro Park | 2017-01-10 |
| 9536793 | Self-aligned gate-first VFETs using a gate spacer recess | John H. Zhang, Kwan-Yong Lim, Chanro Park | 2017-01-03 |