Issued Patents 2005
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6909196 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations | Shubneesh Batra, Michael Chaine, Brent Keeth, Troy A. Manning, Brian Johnson +3 more | 2005-06-21 |
| 6909055 | Electrical device allowing for increased device densities | Warren M. Farnworth, Alan G. Wood, J. Michael Brooks, Eugene H. Cloud | 2005-06-21 |
| 6906417 | Ball grid array utilizing solder balls having a core material covered by a metal layer | Tongbi Jiang | 2005-06-14 |
| 6906402 | High permeability thin films and patterned thin films to reduce noise in high speed interconnections | Leonard Forbes, Kie Y. Ahn | 2005-06-14 |
| 6903444 | High permeability thin films and patterned thin films to reduce noise in high speed interconnections | Leonard Forbes, Kie Y. Ahn | 2005-06-07 |
| 6903003 | High permeability composite films to reduce noise in high speed interconnects | Leonard Forbes, Kie Y. Ahn | 2005-06-07 |
| 6900116 | High permeability thin films and patterned thin films to reduce noise in high speed interconnections | Leonard Forbes, Kie Y. Ahn | 2005-05-31 |
| 6900079 | Method for fabricating a chip scale package using wafer level processing | Larry D. Kinsman | 2005-05-31 |
| 6900077 | Methods of forming board-on-chip packages | — | 2005-05-31 |
| 6899797 | Apparatus for continuous processing of semiconductor wafers | David R. Hembree | 2005-05-31 |
| 6897571 | Method for sawing wafers employing multiple indexing techniques for multiple die dimensions | Derek Gochnour, Michael E. Hess, David R. Hembree | 2005-05-24 |
| 6897667 | Test system for silicon substrate having electrical contacts | — | 2005-05-24 |
| 6893952 | Methods of forming a ball grid array including a non-conductive polymer core and a silver or silver alloy outer layer | Tongbi Jiang | 2005-05-17 |
| 6893961 | Methods for making metallization structures for semiconductor device interconnects | — | 2005-05-17 |
| 6893904 | Stereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposed | — | 2005-05-17 |
| 6890787 | Methods for protecting intermediate conductive elements of semiconductor device assemblies | — | 2005-05-10 |
| 6891248 | Semiconductor component with on board capacitor | Mike Brooks | 2005-05-10 |
| 6887763 | Method for using thin spacers and oxidation in gate oxides | Mohamed A. Ditali | 2005-05-03 |
| 6884706 | High permeability thin films and patterned thin films to reduce noise in high speed interconnections | Leonard Forbes, Kie Y. Ahn | 2005-04-26 |
| 6884658 | Die stacking scheme | — | 2005-04-26 |
| 6881663 | Methods of fabricating silicide pattern structures | Y. Jeff Hu | 2005-04-19 |
| 6882167 | Method of forming an electrical contact | — | 2005-04-19 |
| 6876089 | Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer | Alan G. Wood, Warren M. Farnworth | 2005-04-05 |
| 6873046 | Chip-scale package and carrier for use therewith | Alan G. Wood | 2005-03-29 |
| 6873036 | Die stacking scheme | — | 2005-03-29 |