Issued Patents 2003
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6667557 | Method of forming an apparatus to reduce thermal fatigue stress on flip chip solder connections | David J. Alcoe, Eric A. Johnson, Matthew Reiss | 2003-12-23 |
| 6639302 | Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries | Krishna Darbha, Miguel A. Jimarez, Matthew Reiss, Sanjeev Sathe | 2003-10-28 |
| 6570259 | Apparatus to reduce thermal fatigue stress on flip chip solder connections | David J. Alcoe, Eric A. Johnson, Matthew Reiss | 2003-05-27 |
| 6559666 | Method and device for semiconductor testing using electrically conductive adhesives | William E. Bernier, Michael A. Gaynes, Wayne J. Howell, Mark V. Pierson, Ajit K. Trivedi | 2003-05-06 |
| 6516513 | Method of making a CTE compensated chip interposer | Cynthia S. Milkovich, Mark V. Pierson | 2003-02-11 |
| 6517662 | Process for making semiconductor chip assembly | Thomas M. Culnane, Michael A. Gaynes, Ramesh R. Kodnani, Mark V. Pierson | 2003-02-11 |