Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8355062 | Method and apparatus for processing image | Jing Wang, Yuan Liu, Kai Li | 2013-01-15 |
| 8125035 | CMOS fabrication process | Mahalingam Nandakumar, Amitabh Jain | 2012-02-28 |
| 8101476 | Stress memorization dielectric optimized for NMOS and PMOS | Kanan Garg, Haowen Bu, Mahalingam Nandakumar | 2012-01-24 |
| 7897496 | Semiconductor doping with reduced gate edge diode leakage | Puneet Kohli, Nandakumar Mahalingam, Manoj Mehrotra | 2011-03-01 |
| 7678637 | CMOS fabrication process | Mahalingam Nandakumar, Amitabh Jain | 2010-03-16 |
| 7216310 | Design method and system for optimum performance in integrated circuits that use power management | Amitava Chatterjee, David B. Scott, Theodore W. Houston, Shaoping Tang, Zhiqiang Wu | 2007-05-08 |
| 7211481 | Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer | Manoj Mehrotra, Lahir Shaik Adam, Mahalingam Nandakumar | 2007-05-01 |
| 7029967 | Silicide method for CMOS integrated circuits | Sue Crank, Amitava Chatterjee, Kaiping Liu, Jiong-Ping Lu, Donald Miles +2 more | 2006-04-18 |
| 6855984 | Process to reduce gate edge drain leakage in semiconductor devices | Zhiqiang Wu, Shaoping Tang | 2005-02-15 |
| 6822297 | Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness | Mahalingam Nandakumar, Youngmin Kim | 2004-11-23 |
| 6452236 | Channel implant for improving NMOS ESD robustness | Mahalingam Nadakumar | 2002-09-17 |