Issued Patents All Time
Showing 676–700 of 865 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7526695 | BIST with generator, compactor, controller, adaptor, and separate scan paths | — | 2009-04-28 |
| 7525305 | Core wrappers with input and output linking circuitry | — | 2009-04-28 |
| 7519884 | TAM controller for plural test access mechanisms | — | 2009-04-14 |
| 7516378 | Internal core connected to bond pads by distributor and collector | — | 2009-04-07 |
| 7493536 | IC input memory with dual data and dual control inputs | — | 2009-02-17 |
| 7493535 | JTAG circuit transferring data between devices on TCK terminals | — | 2009-02-17 |
| 7491970 | IC with comparator receiving expected and mask data from pads | Alan Hales | 2009-02-17 |
| 7493537 | Propagation test strobe circuitry with boundary scan circuitry | — | 2009-02-17 |
| 7493538 | Low power scan process with connected stimulus and scan paths | — | 2009-02-17 |
| 7493539 | Separately controlled scan paths of functional registers providing stimulus/response data | — | 2009-02-17 |
| 7467340 | TAP, ST, lockout, and IR SO enable output data control | — | 2008-12-16 |
| 7459926 | Scan distributor loading scan paths simultaneous with loading test data | — | 2008-12-02 |
| 7454677 | Two boundary scan cell switches controlling input to output buffer | — | 2008-11-18 |
| 7453283 | LVDS input circuit with connection to input of output driver | — | 2008-11-18 |
| 7451370 | Input/output buffer test circuitry and leads additional to boundary scan | — | 2008-11-11 |
| 7441170 | External scan circuitry connected to leads extending from core circuitry | — | 2008-10-21 |
| 7437639 | Response bits as stimulus in subdivided scan path delay test | Joel J. Graber | 2008-10-14 |
| 7421633 | Controller receiving combined TMS/TDI and suppyling separate TMS and TDI | — | 2008-09-02 |
| 7417450 | Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit | — | 2008-08-26 |
| 7418643 | Integrated circuit having electrically isolatable test circuitry | Richard L. Antley | 2008-08-26 |
| 7415087 | Circuits with state circuitry having cross connected control inputs | — | 2008-08-19 |
| 7409611 | Wrapper instruction/data register controls from test access or wrapper ports | — | 2008-08-05 |
| 7404127 | Circuitry with multiplexed dedicated and shared scan path cells | — | 2008-07-22 |
| 7404129 | TAP IR control with TAP/WSP or WSP DR control | — | 2008-07-22 |
| 7404128 | Serial data I/O on JTAG TCK with TMS clocking | — | 2008-07-22 |