Issued Patents All Time
Showing 651–675 of 865 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7644330 | Adapting scan architectures for low power operation | — | 2010-01-05 |
| 7629808 | Parallel scan distributors and collectors and process of testing integrated circuits | — | 2009-12-08 |
| 7624321 | IEEE 1149.1 and P1500 test interfaces combined circuits and processes | — | 2009-11-24 |
| 7620867 | IP core design supporting user-added scan register option | — | 2009-11-17 |
| 7617429 | Automatable scan partitioning for low power using external control | Jayashree Saxena | 2009-11-10 |
| 7617430 | Local and global address compare with tap interface TDI/TDO lead | — | 2009-11-10 |
| 7612584 | Simultaneous LVDS I/O signaling method and apparatus | — | 2009-11-03 |
| 7613970 | TAP domain selection circuit with AUXI/O1 or TDI lead | — | 2009-11-03 |
| 7610536 | Select and enable leads connecting IC taps and embedded controller | — | 2009-10-27 |
| 7607058 | Removable and replaceable tap domain selection circuitry | — | 2009-10-20 |
| 7590910 | Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports | Baher Haroun | 2009-09-15 |
| 7587644 | Scan testing using response pattern as stimulus pattern after reset | — | 2009-09-08 |
| 7587648 | Integrated circuit having electrically isolatable test circuitry | Richard L. Antley | 2009-09-08 |
| 7574641 | Probeless testing of pad buffers on wafer | — | 2009-08-11 |
| 7571364 | Selectable JTAG or trace access with data store and output | — | 2009-08-04 |
| 7571365 | Wafer scale testing using a 2 signal JTAG interface | — | 2009-08-04 |
| 7569853 | Test pads on leads unconnected with die pads | Richard L. Antley | 2009-08-04 |
| 7568142 | Boundary scan path method and system with functional and non-functional scan cell memories | — | 2009-07-28 |
| 7555086 | Plural circuit selection using role reversing control inputs | — | 2009-06-30 |
| 7546501 | Selecting test circuitry from header signals on power lead | — | 2009-06-09 |
| 7546503 | Selecting between tap/scan with instructions and lock out signal | — | 2009-06-09 |
| 7546502 | 1114.9 tap linking modules | Baher Haroun, Brian J. Lasher, Anjali Kinra | 2009-06-09 |
| 7541836 | Binary boolean output on input with more than two states | — | 2009-06-02 |
| 7529995 | Second state machine active in first state machine SHIFT-DR state | — | 2009-05-05 |
| 7529996 | DDR input interface to IC test controller circuitry | — | 2009-05-05 |