Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10107859 | Determining test conditions for at-speed transition delay fault tests on semiconductor devices | Jeremy Lee, Pramodchandran Variyam | 2018-10-23 |
| 9103882 | Automatable scan partitioning for low power using external control | Lee D. Whetsel | 2015-08-11 |
| 8769358 | Decoder providing separate clock and enable for scan path segments | Lee D. Whetsel | 2014-07-01 |
| 8539294 | Decode logic driving segmented scan cells with clocks and enables | Lee D. Whetsel | 2013-09-17 |
| 8321729 | Divided scan path segments maintaining test pattern of stimulus/response connections | Lee D. Whetsel | 2012-11-27 |
| 7954030 | Automatable scan partitioning for low power using external control | Lee D. Whetsel | 2011-05-31 |
| 7870451 | Automatable scan partitioning for low power using external control | Lee D. Whetsel | 2011-01-11 |
| 7865849 | System and method for estimating test escapes in integrated circuits | Kenneth M. Butler, John Michael Carulli, Jr., Amit P. Vasavada | 2011-01-04 |
| 7617429 | Automatable scan partitioning for low power using external control | Lee D. Whetsel | 2009-11-10 |
| 7580807 | Test protocol manager for massive multi-site test | Matthew Bullock, Alessandro Paglieri | 2009-08-25 |
| 7324914 | Timing closure for system on a chip using voltage drop based standard delay formats | Atul Jain, Venugopal Puvvada | 2008-01-29 |
| 7219284 | Decode logic selecting IC scan path parts | Lee D. Whetsel | 2007-05-15 |
| 6766487 | Divided scan path with decode logic receiving select control signals | Lee D. Whetsel | 2004-07-20 |
| 6618830 | System and method for pruning a bridging diagnostic list | Hari Balachandran, Ken Butler | 2003-09-09 |