Issued Patents All Time
Showing 376–400 of 865 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8826091 | Die with DIO path, clock input, TLM, and TAP domains | — | 2014-09-02 |
| 8826090 | Test access port and TMS communication circuitry with state machines | — | 2014-09-02 |
| 8826089 | IC state machine controlling communicating data over TDI/TDO or TMS | — | 2014-09-02 |
| 8819510 | Selectable JTAG or trace access with data store and output | — | 2014-08-26 |
| 8817930 | Clock and mode signals for header and data communications | — | 2014-08-26 |
| 8799729 | Multiplexer coupled to second core output and first core input | — | 2014-08-05 |
| 8799712 | TAM with scan frame copy register coupled to input register | — | 2014-08-05 |
| 8769358 | Decoder providing separate clock and enable for scan path segments | Jayashree Saxena | 2014-07-01 |
| 8751887 | Enable gating clock, shift, capture, and update to first gating | — | 2014-06-10 |
| 8751886 | Enable gating select signal to P1500 IR and DR gating | — | 2014-06-10 |
| 8751883 | Selecting an IC core tap linking module for scanning data | — | 2014-06-10 |
| 8751882 | TAP/WRAPPER circuit blocks having two data register control gating circuits | — | 2014-06-10 |
| 8749258 | Parallel scan paths with three bond pads, distributors and collectors | — | 2014-06-10 |
| 8745456 | Controlling user-added boundary scan register with TAP of IP core | — | 2014-06-03 |
| 8742415 | Test circuitry coupled to embedded circuit input/output unconnected to pads | Richard L. Antley | 2014-06-03 |
| 8726111 | Shifting instruction data through IRS of IC TAP and TLM | Baher Haroun, Brian J. Lasher, Anjali Vij | 2014-05-13 |
| 8726110 | Separate dies with interfaces and selection circuitry connected by leads | — | 2014-05-13 |
| 8713390 | JTAG multiplexer with clock/mode input, mode/clock input, and clock output | — | 2014-04-29 |
| 8713389 | Tap and linking module TDO register, gating for TCK and TMS | Baher Haroun | 2014-04-29 |
| 8707116 | Transitioning a state machine through idle, sequence, and unlock states | — | 2014-04-22 |
| 8700963 | Semiconductor test system and method | — | 2014-04-15 |
| 8694844 | AT speed TAP with dual port router and command circuit | — | 2014-04-08 |
| 8692248 | Integrated circuit die having input and output circuit pads, test circuitry, and multiplex circuitry | Alan Hales | 2014-04-08 |
| 8683281 | Scan path delay testing with two memories and three subdivisions | Joel J. Graber | 2014-03-25 |
| 8683279 | Tap instruction register with four bits for TLM selection | — | 2014-03-25 |