Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11307858 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2022-04-19 |
| 11294707 | Global coherence operations | Abhijeet Ashok Chachad, Naveen Bhoria, Neelima Muralidharan | 2022-04-05 |
| 11249842 | Error correcting codes for multi-master memory controller | Abhijeet Ashok Chachad, Son Hung Tran | 2022-02-15 |
| 11243883 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca | 2022-02-08 |
| 11237905 | Pipelined read-modify-write operations in cache memory | Abhijeet Ashok Chachad, Daniel Wu | 2022-02-01 |
| 11194617 | Merging data for write allocate | Abhijeet Ashok Chachad | 2021-12-07 |
| 11169924 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, Abhijeet Ashok Chachad, Hung Ong | 2021-11-09 |
| 11144456 | Hardware coherence signaling protocol | Abhijeet Ashok Chachad, Naveen Bhoria, Peter Michael Hippleheuser | 2021-10-12 |
| 11138117 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca | 2021-10-05 |
| 11119776 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2021-09-14 |
| 11106583 | Shadow caches for level 2 cache controller | Abhijeet Ashok Chachad, Naveen Bhoria | 2021-08-31 |
| 11106584 | Hardware coherence for memory controller | Abhijeet Ashok Chachad, Naveen Bhoria | 2021-08-31 |
| 10795844 | Multicore bus architecture with non-blocking high performance transaction credit system | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2020-10-06 |
| 10642742 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, Abhijeet Ashok Chachad, Hung Ong | 2020-05-05 |
| 10606596 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2020-03-31 |
| 10599433 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2020-03-24 |
| 10489305 | Prefetch kill and revival in an instruction cache | Bipin Prasad Heremagalur Ramaprasad, Abhijeet Ashok Chachad, Hung Ong | 2019-11-26 |
| 10311007 | Multicore bus architecture with non-blocking high performance transaction credit system | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2019-06-04 |
| 9904645 | Multicore bus architecture with non-blocking high performance transaction credit system | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2018-02-27 |
| 9575901 | Programmable address-based write-through cache control | Raguram Damodaran, Abhijeet Ashok Chachad, Naveen Bhoria | 2017-02-21 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +2 more | 2017-01-31 |
| 9268708 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Raguram Damodaran, Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran | 2016-02-23 |
| 9009408 | Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system | Abhijeet Ashok Chachad, Raguram Damodaran | 2015-04-14 |
| 9003122 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Raguram Damodaran, Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran | 2015-04-07 |
| 8683137 | Cache pre-allocation of ways for pipelined allocate requests | Abhijeet Ashok Chachad | 2014-03-25 |