Issued Patents All Time
Showing 101–125 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8549455 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same | Jonathan R. Quandt, Dhrumil Gandhi | 2013-10-01 |
| 8471391 | Methods for multi-wire routing and apparatus implementing same | Daryl Fox | 2013-06-25 |
| 8453094 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Stephen Kornachuk, Jim Mali, Carole Lambert | 2013-05-28 |
| 8448102 | Optimizing layout of irregular structures in regular layout context | Stephen Kornachuk, Carole Lambert, James Mali, Brian Reed | 2013-05-21 |
| 8436400 | Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length | Michael C. Smayling | 2013-05-07 |
| 8405162 | Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region | Jim Mali, Carole Lambert | 2013-03-26 |
| 8405163 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature | Jim Mali, Carole Lambert | 2013-03-26 |
| 8395224 | Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes | Jim Mali, Carole Lambert | 2013-03-12 |
| 8356268 | Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings | Michael C. Smayling | 2013-01-15 |
| 8286107 | Methods and systems for process compensation technique acceleration | Michael C. Smayling, Michael A. McAweeney | 2012-10-09 |
| 8283701 | Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos | Michael C. Smayling | 2012-10-09 |
| 8274099 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications | — | 2012-09-25 |
| 8264009 | Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length | Michael C. Smayling | 2012-09-11 |
| 8264049 | Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature | — | 2012-09-11 |
| 8264044 | Integrated circuit including cross-coupled transistors having two complementary pairs of co-aligned gate electrodes with offset contacting structures positioned between transistors of different type | — | 2012-09-11 |
| 8264008 | Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size | Michael C. Smayling | 2012-09-11 |
| 8264007 | Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances | Michael C. Smayling | 2012-09-11 |
| 8258581 | Integrated circuit including cross-coupled transistors with two transistors of different type formed by same gate level structure and two transistors of different type formed by separate gate level structures | — | 2012-09-04 |
| 8258552 | Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends | Michael C. Smayling | 2012-09-04 |
| 8258551 | Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction | Michael C. Smayling | 2012-09-04 |
| 8258550 | Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact | Michael C. Smayling | 2012-09-04 |
| 8258549 | Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length | Michael C. Smayling | 2012-09-04 |
| 8258548 | Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region | Michael C. Smayling | 2012-09-04 |
| 8258547 | Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts | Michael C. Smayling | 2012-09-04 |
| 8253173 | Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region | Michael C. Smayling | 2012-08-28 |