Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754878 | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires | Stephen Kornachuk, James Mali, Carole Lambert, Scott T. Becker | 2017-09-05 |
| 9122832 | Methods for controlling microloading variation in semiconductor wafer layout and fabrication | Michael C. Smayling, Scott T. Becker | 2015-09-01 |
| 9070431 | Memory circuitry with write assist | Frank Guo, Martin Jay Kinkade, Bo Zheng, Shrisagar Dwivedi | 2015-06-30 |
| 8680912 | Level shifting circuitry | — | 2014-03-25 |
| 8448102 | Optimizing layout of irregular structures in regular layout context | Stephen Kornachuk, Carole Lambert, James Mali, Scott T. Becker | 2013-05-21 |
| 8225239 | Methods for defining and utilizing sub-resolution features in linear topology | Michael C. Smayling, Joseph Hong, Stephen R. Fairbanks, Scott T. Becker | 2012-07-17 |
| 7005910 | Feed-forward circuit for reducing delay through an input buffer | Scott T. Becker, Puneet Sawhney, Jayanth Thyamagundlam | 2006-02-28 |
| 6924687 | Voltage tolerant circuit for protecting an input buffer | Puneet Sawhney, Jayanth Thyamagundlam, Scott T. Becker | 2005-08-02 |