Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754878 | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires | Stephen Kornachuk, Carole Lambert, Scott T. Becker, Brian Reed | 2017-09-05 |
| 8448102 | Optimizing layout of irregular structures in regular layout context | Stephen Kornachuk, Carole Lambert, Brian Reed, Scott T. Becker | 2013-05-21 |
| 6470304 | Method and apparatus for eliminating bitline voltage offsets in memory devices | Scott T. Becker | 2002-10-22 |
| 6016390 | Method and apparatus for eliminating bitline voltage offsets in memory devices | Scott T. Becker | 2000-01-18 |