Issued Patents All Time
Showing 51–75 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9035359 | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods | Michael C. Smayling | 2015-05-19 |
| 9009641 | Circuits with linear finfet structures | Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt +1 more | 2015-04-14 |
| 8966424 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same | Jonathan R. Quandt, Dhrumil Gandhi | 2015-02-24 |
| 8952425 | Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length | Michael C. Smayling | 2015-02-10 |
| 8946781 | Integrated circuit including gate electrode conductive structures with different extension distances beyond contact | Michael C. Smayling | 2015-02-03 |
| 8921896 | Integrated circuit including linear gate electrode structures having different extension distances beyond contact | Michael C. Smayling | 2014-12-30 |
| 8921897 | Integrated circuit with gate electrode conductive structures having offset ends | Michael C. Smayling | 2014-12-30 |
| 8872283 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature | Jim Mali, Carole Lambert | 2014-10-28 |
| 8866197 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature | Jim Mali, Carole Lambert | 2014-10-21 |
| 8863063 | Finfet transistor circuit | Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt +1 more | 2014-10-14 |
| 8853793 | Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends | Jim Mali, Carole Lambert | 2014-10-07 |
| 8853794 | Integrated circuit within semiconductor chip including cross-coupled transistor configuration | Jim Mali, Carole Lambert | 2014-10-07 |
| 8847329 | Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts | Jim Mali, Carole Lambert | 2014-09-30 |
| 8847331 | Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures | Jim Mali, Carole Lambert | 2014-09-30 |
| 8836045 | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track | Jim Mali, Carole Lambert | 2014-09-16 |
| 8839175 | Scalable meta-data objects | Michael C. Smayling, Daryl Fox, Jonathan R. Quandt | 2014-09-16 |
| 8835989 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications | Jim Mali, Carole Lambert | 2014-09-16 |
| 8823062 | Integrated circuit with offset line end spacings in linear gate electrode level | Michael C. Smayling | 2014-09-02 |
| 8816402 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor | Jim Mali, Carole Lambert | 2014-08-26 |
| 8785979 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer | Jim Mali, Carole Lambert | 2014-07-22 |
| 8785978 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer | Jim Mali, Carole Lambert | 2014-07-22 |
| 8772839 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer | Jim Mali, Carole Lambert | 2014-07-08 |
| 8759985 | Methods for multi-wire routing and apparatus implementing same | Daryl Fox | 2014-06-24 |
| 8759882 | Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos | Michael C. Smayling | 2014-06-24 |
| 8756551 | Methods for designing semiconductor device with dynamic array section | Michael C. Smayling | 2014-06-17 |