Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11538507 | Header circuit placement in memory device | Po-Sheng Wang, Kao-Cheng Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2022-12-27 |
| 11373702 | Boost schemes for write assist | Wei-jer Hsieh, Chiting Cheng, Shang-Chi Wu | 2022-06-28 |
| 11342340 | Layout of static random access memory periphery circuit | Chi-Lung Lee, Chien-Chi TIEN, Chiting Cheng | 2022-05-24 |
| 11323101 | Clock circuit and method of operating the same | Hao-I Yang, Fu-An Wu, Chiting Cheng, Cheng Hung Lee, Chen-Lin Yang | 2022-05-03 |
| 11301148 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2022-04-12 |
| 11264066 | Leakage pathway prevention in a memory storage device | Shang-Chi Wu, Cheng Hung Lee, Chien-Kuo Su, Chiting Cheng, Yu-Hao Hsu | 2022-03-01 |
| 11199866 | Voltage regulator with power rail tracking | Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yu-Hao Hsu, Yen-Huei Chen +2 more | 2021-12-14 |
| 11200926 | Dual rail memory, memory macro and associated hybrid power supply method | Chiting Cheng | 2021-12-14 |
| 11189341 | Memory device with fly word line | Chiting Cheng | 2021-11-30 |
| 10951200 | Clock circuit and method of operating the same | Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu | 2021-03-16 |
| 10949100 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2021-03-16 |
| 10878855 | Low cell voltage (LCV) memory write assist | Chiting Cheng, Wei-jer Hsieh | 2020-12-29 |
| 10872659 | Memory system having write assist circuit including memory-adapted transistors | Chiting Cheng, Jonathan Tsung-Yung Chang, Shang-Chi Wu | 2020-12-22 |
| 10867646 | Bit line logic circuits and methods | Shang-Chi Wu, Chiting Cheng, Jonathan Tsung-Yung Chang, Mahmut Sinangil | 2020-12-15 |
| 10847210 | Memory device with fly word line | Chiting Cheng | 2020-11-24 |
| 10818677 | Layout of static random access memory periphery circuit | Chi-Lung Lee, Chien-Chi TIEN, Chiting Cheng | 2020-10-27 |
| 10811085 | Dual rail device with power detector | Chiting Cheng | 2020-10-20 |
| 10762934 | Leakage pathway prevention in a memory storage device | Shang-Chi Wu, Cheng Hung Lee, Chien-Kuo Su, Chiting Cheng, Yu-Hao Hsu | 2020-09-01 |
| 10622039 | Dual rail memory with bist circuitry, memory macro and associated hybrid power supply method | Chiting Cheng | 2020-04-14 |
| 10574213 | Clock circuit and method of operating the same | Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu | 2020-02-25 |
| 10553275 | Device having write assist circuit including memory-adapted transistors and method for making the same | Chiting Cheng, Jonathan Tsung-Yung Chang, Shang-Chi Wu | 2020-02-04 |
| 10503421 | Configurable memory storage system | Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu +6 more | 2019-12-10 |
| 10490263 | Dual rail device with power detector | Chiting Cheng | 2019-11-26 |
| 10340897 | Clock generating circuit and method of operating the same | Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu | 2019-07-02 |
| 10263621 | Level shifter with improved voltage difference | Shang-Chi Wu, Chiting Cheng, Wei-jer Hsieh | 2019-04-16 |