Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163470 | Dual rail memory, memory macro and associated hybrid power supply method | Chiting Cheng | 2018-12-25 |
| 10141045 | Dual rail device with power detector for controlling power to first and second power domains | Chiting Cheng | 2018-11-27 |
| 9659603 | Power management circuit for an electronic device | Hektor Huang, Yu-Hao Hsu, Chia-En Huang, Chiting Cheng, Chen-Lin Yang +2 more | 2017-05-23 |
| 9489991 | Memory reading circuit, memory device and method of operating memory device | Hsin-Hsin Ko, Chiting Cheng, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-11-08 |
| 9437281 | Negative bitline boost scheme for SRAM write-assist | Wei-jer Hsieh, Hsiao Wen Lu, Chiting Cheng, Jonathan Tsung-Yung Chang | 2016-09-06 |
| 9324453 | Memory unit and method of testing the same | Wei-jer Hsieh, Hong-Chen Cheng, Chiting Cheng, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-04-26 |
| 9324413 | Write assist circuit, memory device and method | Hsin-Hsin Ko, Chiting Cheng, Cheng Hung Lee, Jonathan Tsung-Yung Chang | 2016-04-26 |
| 9305635 | High density memory structure | Hsiao Wen Lu, Chiting Cheng, Jonathan Tsung-Yung Chang | 2016-04-05 |
| 9070432 | Negative bitline boost scheme for SRAM write-assist | Wei-jer Hsieh, Hsiao Wen Lu, Chiting Cheng, Jonathan Tsung-Yung Chang | 2015-06-30 |
| 8923078 | Voltage divider control circuit | Hsin-Hsin Ko, Chiting Cheng, Jonathan Tsung-Yung Chang | 2014-12-30 |
| 8575965 | Internal clock gating apparatus | Chi-Lin Liu, Chung-Cheng Chou, Hsiao Wen Lu | 2013-11-05 |