Issued Patents All Time
Showing 76–100 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10276559 | System and method of fabricating ESD FinFET with improved metal landing in the drain | Tzung-Chi Lee, Bao-Ru Young, Yung Feng Chang | 2019-04-30 |
| 10276445 | Leakage reduction methods and structures thereof | Chia-Sheng Fan, Chun-Yen Lin, Bao-Ru Young | 2019-04-30 |
| 10269785 | Conductive line patterning | Ru-Gun Liu, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting | 2019-04-23 |
| 10204202 | Dummy fin cell placement in an integrated circuit layout | Bao-Ru Young, Yu-Jung Chang, Tzung-Chi Lee | 2019-02-12 |
| 10164034 | Semiconductor device and a method for fabricating the same | Yi-Jyun Huang, Bao-Ru Young | 2018-12-25 |
| 10141296 | Dummy fin cell placement in an integrated circuit layout | Tzung-Chi Lee, Yu-Jung Chang, Bao-Ru Young | 2018-11-27 |
| 10079289 | Metal gate structure and methods thereof | Tzung-Chi Lee, Bao-Ru Young, Chia-Sheng Fan | 2018-09-18 |
| 9995998 | Method and apparatus for integrated circuit layout | Yi-Fan Chen, Chin-Shan Hou, Yu-Bey Wu | 2018-06-12 |
| 9991158 | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device | Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien +1 more | 2018-06-05 |
| 9984191 | Cell layout and structure | Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu +2 more | 2018-05-29 |
| 9899263 | Method of forming layout design | Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang, Ting-Wei Chiang +1 more | 2018-02-20 |
| 9865589 | System and method of fabricating ESD FinFET with improved metal landing in the drain | Tzung-Chi Lee, Bao-Ru Young, Yung Feng Chang | 2018-01-09 |
| 9859364 | Semiconductor device and manufacturing method thereof | Sheng-Hsiung Wang, Bao-Ru Young | 2018-01-02 |
| 9806071 | Integrated circuit with elongated coupling | Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2017-10-31 |
| 9773879 | Semiconductor device and a method for fabricating the same | Yi-Jyun Huang, Bao-Ru Young | 2017-09-26 |
| 9691721 | Jog design in integrated circuits | Tsung-Lin Wu, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Hsu | 2017-06-27 |
| 9472501 | Conductive line patterning | Ru-Gun Liu, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting | 2016-10-18 |
| 9431381 | System and method of processing cutting layout and example switching circuit | Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien | 2016-08-30 |
| 9425141 | Integrated circuit with elongated coupling | Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2016-08-23 |
| 9412883 | Methods and apparatus for MOS capacitors in replacement gate process | Pai-Chieh Wang, Yimin Huang, Chung-Hui Chen | 2016-08-09 |
| 9412700 | Semiconductor device and method of manufacturing semiconductor device | Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2016-08-09 |
| 9391056 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting +1 more | 2016-07-12 |
| 9377680 | Method and apparatus for integrated circuit layout | Yi-Fan Chen, Chin-Shan Hou, Yu-Bey Wu | 2016-06-28 |
| 9355912 | Jog design in integrated circuits | Tsung-Lin Wu, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Hsu | 2016-05-31 |
| 9336348 | Method of forming layout design | Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang, Ting-Wei Chiang +1 more | 2016-05-10 |