Issued Patents All Time
Showing 51–75 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10998304 | Conductive line patterning | Ru-Gun Liu, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting | 2021-05-04 |
| 10991691 | Semiconductor device having fins and an isolation region | Chia-Sheng Fan, Bao-Ru Young | 2021-04-27 |
| 10971588 | Semiconductor device including FinFET with self-align contact | Yi-Jyun Huang, Bao-Ru Young | 2021-04-06 |
| 10957604 | Semiconductor device and method | Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao +1 more | 2021-03-23 |
| 10943054 | Integrated circuit layouts with line-end extensions | Hsien-Huang Liao, Bao-Ru Young, Yung Feng Chang | 2021-03-09 |
| 10867101 | Leakage reduction between two transistor devices on a same continuous fin | Chun-Yen Lin, Bao-Ru Young | 2020-12-15 |
| 10854512 | Method and IC design with non-linear power rails | Sheng-Hsiung Wang, Bao-Ru Young | 2020-12-01 |
| 10832958 | Leakage reduction methods and structures thereof | Chia-Sheng Fan, Chun-Yen Lin, Bao-Ru Young | 2020-11-10 |
| 10803227 | Integrated circuit layouts with line-end extensions | Hsien-Huang Liao, Bao-Ru Young, Yung Feng Chang | 2020-10-13 |
| 10720361 | Methods and apparatus for MOS capacitors in replacement gate process | Pai-Chieh Wang, Yimin Huang, Chung-Hui Chen | 2020-07-21 |
| 10664639 | Cell layout and structure | Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu +2 more | 2020-05-26 |
| 10658486 | Mitigation of time dependent dielectric breakdown | Yi-Jyun Huang, Bao-Ru Young | 2020-05-19 |
| 10535746 | Metal gate structure and methods thereof | Tzung-Chi Lee, Bao-Ru Young, Chia-Sheng Fan | 2020-01-14 |
| 10522634 | Finfet with self-aligned source/drain | Yi-Jyun Huang, Bao-Ru Young | 2019-12-31 |
| 10522681 | Method of forming a FinFET having a relaxation prevention anchor | Sheng-Hsiung Wang, Yung Feng Chang | 2019-12-31 |
| 10522527 | System and method of processing cutting layout and example switching circuit | Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien | 2019-12-31 |
| 10515957 | Semiconductor device having fins | Chia-Sheng Fan, Bao-Ru Young | 2019-12-24 |
| 10515850 | Method and IC design with non-linear power rails | Sheng-Hsiung Wang, Bao-Ru Young | 2019-12-24 |
| 10504837 | Semiconductor device including a conductive feature over an active region | Hui-Zhong Zhuang, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Wang, Li-Chun Tien | 2019-12-10 |
| 10453837 | System and method of fabricating ESD finFET with improved metal landing in the drain | Tzung-Chi Lee, Bao-Ru Young, Yung Feng Chang | 2019-10-22 |
| 10354920 | Methods and apparatus for MOS capacitors in replacement gate process | Pai-Chieh Wang, Yimin Huang, Chung-Hui Chen | 2019-07-16 |
| 10354997 | Method for manufacturing semiconductor device with replacement gates | Chia-Sheng Fan, Bao-Ru Young | 2019-07-16 |
| 10340348 | Method of manufacturing finFETs with self-align contacts | Yi-Jyun Huang, Bao-Ru Young | 2019-07-02 |
| 10283495 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Chun-Yi Lee, Jyh-Kang Ting, Juing-Yi Wu, Liang-Yao Lee +1 more | 2019-05-07 |
| 10276718 | FinFET having a relaxation prevention anchor | Sheng-Hsiung Wang, Yung Feng Chang | 2019-04-30 |