Issued Patents All Time
Showing 51–75 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9825036 | Structure and method for semiconductor device | Yi-Jing Lee, Ming-Hua Yu | 2017-11-21 |
| 9806171 | Method for making source and drain regions of a MOSFET with embedded germanium-containing layers having different germanium concentration | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2017-10-31 |
| 9768178 | Semiconductor device, static random access memory cell and manufacturing method of semiconductor device | Yi-Jing Lee, Ming-Hua Yu, Kun-Mu Li | 2017-09-19 |
| 9755077 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2017-09-05 |
| 9698243 | Transistor strain-inducing scheme | Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2017-07-04 |
| 9691898 | Germanium profile for channel strain | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2017-06-27 |
| 9666691 | Epitaxy profile engineering for FinFETs | Chien-Chang Su, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen | 2017-05-30 |
| 9666686 | MOS devices having epitaxy regions with reduced facets | Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee | 2017-05-30 |
| 9601619 | MOS devices with non-uniform P-type impurity profile | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2017-03-21 |
| 9601574 | V-shaped epitaxially formed semiconductor layer | Ming-Hua Yu, Chii-Horng Li | 2017-03-21 |
| 9583483 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2017-02-28 |
| 9525026 | Method of forming an epitaxial semiconductor layer in a recess and a semiconductor device having the same | Chun Hsiung Tsai | 2016-12-20 |
| 9515187 | Controlling the shape of source/drain regions in FinFETs | Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin | 2016-12-06 |
| 9496149 | Semiconductor devices and methods for manufacturing the same | Chun Hsiung Tsai | 2016-11-15 |
| 9373695 | Method for improving selectivity of epi process | Kuan-Yu Chen, Hsien-Hsin Lin, Chun-Feng Nieh, Hsueh-Chang Sung, Chien-Chang Su | 2016-06-21 |
| 9362360 | Modulating germanium percentage in MOS devices | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2016-06-07 |
| 9356150 | Method for incorporating impurity element in EPI silicon process | Chien-Chang Su, Hsien-Hsin Lin, Kuan-Yu Chen, Hsueh-Chang Sung, Yi-Fang Pai | 2016-05-31 |
| 9337337 | MOS device having source and drain regions with embedded germanium-containing diffusion barrier | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2016-05-10 |
| 9287398 | Transistor strain-inducing scheme | Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2016-03-15 |
| 9209020 | Method of forming an epitaxial semiconductor layer in a recess and a semiconductor device having the same | Chun Hsiung Tsai | 2015-12-08 |
| 9209175 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2015-12-08 |
| 9142643 | Method for forming epitaxial feature | Yu-Hung Cheng, Chun Hsiung Tsai, Jeff J. Xu | 2015-09-22 |
| 9117905 | Method for incorporating impurity element in EPI silicon process | Chien-Chang Su, Hsien-Hsin Lin, Kuan-Yu Chen, Hsueh-Chang Sung, Yi-Fang Pai | 2015-08-25 |
| 9117745 | Mechanisms for forming stressor regions in a semiconductor device | Chun Hsiung Tsai, Tsan-Chun Wang, Su-Hao Liu, Chii-Ming Wu | 2015-08-25 |
| 9076734 | Defect reduction for formation of epitaxial layer in source and drain regions | Chun Hsiung Tsai, Chien-Chang Su | 2015-07-07 |