Issued Patents All Time
Showing 26–50 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10861971 | Doping profile for strained source/drain region | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2020-12-08 |
| 10797173 | MOS devices with non-uniform p-type impurity profile | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2020-10-06 |
| 10749029 | Semiconductor device and manufacturing method thereof | Kun-Mu Li, Ming-Hua Yu, Chan-Lon Yang | 2020-08-18 |
| 10734520 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2020-08-04 |
| 10727342 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2020-07-28 |
| 10727229 | Structure and method for semiconductor device | Yi-Jing Lee, Ming-Hua Yu | 2020-07-28 |
| 10714487 | Semiconductor device and manufacturing method of a semiconductor device | Yi-Jing Lee, Ming-Hua Yu, Kun-Mu Li | 2020-07-14 |
| 10546784 | Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same | Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Ming-Hua Yu | 2020-01-28 |
| 10510753 | Integrated circuit and manufacturing method thereof | Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu | 2019-12-17 |
| 10475926 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2019-11-12 |
| 10269577 | Semiconductor devices and methods for manufacturing the same | Chun Hsiung Tsai | 2019-04-23 |
| 10170483 | Semiconductor device, static random access memory cell and manufacturing method of semiconductor device | Yi-Jing Lee, Ming-Hua Yu, Kun-Mu Li | 2019-01-01 |
| 10164096 | Semiconductor device and manufacturing method thereof | Kun-Mu Li, Ming-Hua Yu, Chan-Lon Yang | 2018-12-25 |
| 10158016 | MOS devices with non-uniform p-type impurity profile | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2018-12-18 |
| 10084089 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2018-09-25 |
| 10062781 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2018-08-28 |
| 10049936 | Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same | Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Ming-Hua Yu | 2018-08-14 |
| 10014411 | Modulating germanium percentage in MOS devices | Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee | 2018-07-03 |
| 9991364 | Transistor strain-inducing scheme | Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2018-06-05 |
| 9922975 | Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof | Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu | 2018-03-20 |
| 9911826 | Devices with strained source/drain structures | Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin | 2018-03-06 |
| 9905646 | V-shaped epitaxially formed semiconductor layer | Ming-Hua Yu, Chii-Horng Li | 2018-02-27 |
| 9853155 | MOS devices having epitaxy regions with reduced facets | Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee | 2017-12-26 |
| 9847225 | Semiconductor device and method of manufacturing the same | Chun-Fai Cheng, An-Shen Chang, Hui-Min Lin, Hsien-Ching Lo | 2017-12-19 |
| 9842910 | Methods for manufacturing devices with source/drain structures | Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin | 2017-12-12 |