Issued Patents All Time
Showing 201–225 of 268 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9514796 | Magnetic storage cell memory with back hop-prevention | Charles Augustine, Shigeki Tomishima, Wei Wu, James W. Tschanz, Georgios Panagopoulos +1 more | 2016-12-06 |
| 9418723 | Techniques to reduce memory cell refreshes for a memory device | Zeshan A. Chishti, Ishwar Bhati | 2016-08-16 |
| 9378021 | Instruction and logic for run-time evaluation of multiple prefetchers | Zeshan A. Chishti, Christopher B. Wilkerson, Seth H. Pugsley, Peng-Fei Chuang, Robert L. Scott +2 more | 2016-06-28 |
| 9335996 | Recycling error bits in floating point units | Helia Naeimi, Ralph Nathan, Daniel Sorin | 2016-05-10 |
| 9299412 | Write operations in spin transfer torque memory | Helia Naeimi, Charles Augustine | 2016-03-29 |
| 9286224 | Constraining prefetch requests to a processor socket | Seth H. Pugsley, Robert L. Scott, Zeshan A. Chishti, Peng-Fei Chuang, Khun Ban +2 more | 2016-03-15 |
| 9251095 | Providing metadata in a translation lookaside buffer (TLB) | David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar | 2016-02-02 |
| 9223544 | Number representation and memory system for arithmetic | Helia Naeimi, Ralph Nathan, John L. Gustafson | 2015-12-29 |
| 9189014 | Sequential circuit with error detection | Keith Alan Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson +2 more | 2015-11-17 |
| 9047171 | Differentiating cache reliability to reduce minimum on-die voltage | Zhen Fang, Ravishankar Iyer, Srihari Makineni | 2015-06-02 |
| 9043674 | Error detection and correction apparatus and method | Wei Wu, Rajat Agarwal, Henry Stracovsky | 2015-05-26 |
| 8966345 | Selective error correction in memory to reduce power consumption | Christopher B. Wilkerson, Alaa R. Alameldeen | 2015-02-24 |
| 8848858 | Integrated non-volatile monotonic counters | James W. Tschanz, Christopher B. Wilkerson, Scott H. Robinson | 2014-09-30 |
| 8819392 | Providing metadata in a translation lookaside buffer (TLB) | David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar | 2014-08-26 |
| 8762821 | Method of correcting adjacent errors by using BCH-based error correction coding | Wei Wu, Muhammad M. Khellah | 2014-06-24 |
| 8640005 | Method and apparatus for using cache memory in a system that supports a low power state | Christopher B. Wilkerson, Alaa R. Alameldeen, Zeshan A. Chishti, Dinesh Somasekhar, Wei Wu | 2014-01-28 |
| 8539303 | Low overhead error correcting code protection for stored information | Dinesh Somasekhar | 2013-09-17 |
| 8533572 | Error correcting code logic for processor caches that uses a common set of check bits | Wei Wu | 2013-09-10 |
| 8301970 | Sequential circuit with error detection | Keith Alan Bowman, James Tachanz, Nam Sung Kim, Janice C. Lee, Chris Wilkerson +2 more | 2012-10-30 |
| 8250334 | Providing metadata in a translation lookaside buffer (TLB) | David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar | 2012-08-21 |
| 8245111 | Performing multi-bit error correction on a cache line | Zeshan A. Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Dinesh Somasekhar +1 more | 2012-08-14 |
| 8125246 | Method and apparatus for late timing transition detection | Edward T. Grochowski, Chris Wilkerson, Murali Annavaram | 2012-02-28 |
| 7958336 | System and method for reservation station load dependency matrix | Sagi Lahav, Guy Patkin, Zeev Sperber, Herbert Hum, Srikanth Srinivasan | 2011-06-07 |
| 7941631 | Providing metadata in a translation lookaside buffer (TLB) | David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar | 2011-05-10 |
| 7653850 | Delay fault detection using latch with error sampling | James W. Tschanz, Keith Alan Bowman, Nam Sung Kim, Chris Wilkerson, Tanay Karnik | 2010-01-26 |