Issued Patents All Time
Showing 251–268 of 268 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6691222 | Non-stalling circular counterflow pipeline processor with recorder buffer | Kenneth J. Janik, Michael F. Miller | 2004-02-10 |
| 6690604 | Register files and caches with digital sub-threshold leakage current calibration | Steven Hsu, Ram Krishnamurthy | 2004-02-10 |
| 6671780 | Modified least recently allocated cache replacement method and apparatus that allows skipping a least recently allocated cache block | Konrad K. Lai | 2003-12-30 |
| 6643199 | Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports | Stephen H. Tang, Steven Hsu, Vivek K. De | 2003-11-04 |
| 6608775 | Register file scheme | Konrad K. Lai | 2003-08-19 |
| 6567329 | Multiple word-line accessing and accessor | Dinesh Somasekhar, Vivek K. De | 2003-05-20 |
| 6553485 | Non-stalling circular counterflow pipeline processor with reorder buffer | Kenneth J. Janik, Michael F. Miller | 2003-04-22 |
| 6538517 | Frequency phase detector for differentiating frequencies having small phase differences | — | 2003-03-25 |
| 6496402 | Noise suppression for open bit line DRAM architectures | Dinesh Somasekhar, Vivek K. De | 2002-12-17 |
| 6441648 | Double data rate dynamic logic | Steven Hsu, Ram Krishnamurthy | 2002-08-27 |
| 6430083 | Register file scheme | Konrad K. Lai | 2002-08-06 |
| 6421269 | Low-leakage MOS planar capacitors for use within DRAM storage cells | Dinesh Somasekhar, Vivek K. De | 2002-07-16 |
| 6421289 | Method and apparatus for charge-transfer pre-sensing | Dinesh Somasekhar | 2002-07-16 |
| 6359802 | One-transistor and one-capacitor DRAM cell for logic process technology | Vivek K. De | 2002-03-19 |
| 6351805 | Non-stalling circular counterflow pipeline processor with reorder buffer | Kenneth J. Janik, Michael F. Miller | 2002-02-26 |
| 6247115 | Non-stalling circular counterflow pipeline processor with reorder buffer | Kenneth J. Janik, Michael F. Miller | 2001-06-12 |
| 6163839 | Non-stalling circular counterflow pipeline processor with reorder buffer | Kenneth J. Janik, Michael F. Miller | 2000-12-19 |
| 6154045 | Method and apparatus for reducing signal transmission delay using skewed gates | Yibin Ye, Vivek K. De, Siva G. Narendra | 2000-11-28 |