Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9490006 | Time division multiplexed multiport memory | XiuLi YANG, He-Zhou WAN, Ming-En Bu, Ching-Wei Wu | 2016-11-08 |
| 9449139 | System and method for tracing a net | Ming Feng, Li Huang, Zhen Chen, Ya Zhang | 2016-09-20 |
| 9372954 | Semiconductor device design system and method | Ya Zhang, Ming Feng, Peng-Sheng Chen | 2016-06-21 |
| 9342646 | Method, system and computer readable medium using stitching for mask assignment of patterns | Hsien Yu-Tseng, Shih-Kai Lin, Chin-Shen Lin, Yu Jiang, Heng-Kai Liu +1 more | 2016-05-17 |
| 9305134 | Semiconductor device design method, system and computer program product | Chih Chi Hsiao, Wei-Ting Lin, Tsung-Hsin Yu, Chien-Wen Chen, Yung-Chow Peng | 2016-04-05 |
| 9245078 | Integrated circuit design system | Yu Jiang, Chien-Wen Chen | 2016-01-26 |
| 9245615 | Boost system for dual-port SRAM | Ching-Wei Wu, He-Zhou WAN, Ming-En Bu, XiuLi YANG, Cheng Hung Lee | 2016-01-26 |
| 8978000 | Performance-driven and gradient-aware dummy insertion for gradient-sensitive array | Hsiao-Hui Chen, Cheok-Kei Lei, Po-Tsun Chen, Yu Jiang | 2015-03-10 |
| 8904326 | Semiconductor device design method, system and computer program product | Chih Chi Hsiao, Wei-Ting Lin, Tsung-Hsin Yu, Chien-Wen Chen, Yung-Chow Peng | 2014-12-02 |
| 8806414 | Method and system for layout parasitic estimation | Yu Jiang, Yi-Ting Lin, Hsien Yu Tseng, Heng-Kai Liu, Chien-Wen Chen +1 more | 2014-08-12 |
| 8775993 | Integrated circuit design flow with layout-dependent effects | Yu Jiang, Chien-Wen Chen | 2014-07-08 |
| 8745552 | EDA tool and method, and integrated circuit formed by the method | Hsien Yu Tseng, Shih-Kai Lin, Chin-Shen Lin, Yu Jiang, Heng-Kai Liu +1 more | 2014-06-03 |
| 8726207 | On-the-fly device characterization from layouts of circuits | Yu Jiang, Ya-Li Tai, Chien-Wen Chen, Chauchin Su | 2014-05-13 |
| 7498885 | Voltage controlled oscillator with gain compensation | — | 2009-03-03 |
| 7464346 | Method for designing phase-lock loop circuits | Chien-Hung Chen, Chih-Chiang Chang | 2008-12-09 |
| 7113560 | Serial link scheme based on delay lock loop | Linhsiang Wei, Fu-Shing Ju | 2006-09-26 |
| 7010770 | Method of wide wire identification | Eric Keng-Hao Liang | 2006-03-07 |