Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8806414 | Method and system for layout parasitic estimation | Mu-Jen Huang, Yu Jiang, Yi-Ting Lin, Hsien Yu Tseng, Heng-Kai Liu +1 more | 2014-08-12 |
| 8726207 | On-the-fly device characterization from layouts of circuits | Yu Jiang, Ya-Li Tai, Mu-Jen Huang, Chien-Wen Chen | 2014-05-13 |
| 7764086 | Buffer circuit | Hung-Wen Lu | 2010-07-27 |
| 7228479 | IEEE Std. 1149.4 compatible analog BIST methodology | Shyh-Horng Lin, Laung-Terng Wang | 2007-06-05 |