Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11107902 | Dielectric spacer to prevent contacting shorting | Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Shu-Yuan Ku, Fu-Kai Yang +2 more | 2021-08-31 |
| 10991628 | Etch stop layer between substrate and isolation structure | Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen | 2021-04-27 |
| 10978351 | Etch stop layer between substrate and isolation structure | Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen | 2021-04-13 |
| 10901771 | Methods and systems for securely and efficiently clustering distributed processes using a consistent database | Srinivas Neginhal, Medhavi Dhawan, Vjekoslav Brajkovic, Cheng Zhang, Jiaqi Chen +5 more | 2021-01-26 |
| 10868003 | Creating devices with multiple threshold voltages by cut-metal-gate process | Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin | 2020-12-15 |
| 10741450 | Semiconductor device having a metal gate and formation method thereof | Chang-Yun Chang, Bone-Fong Wu, Ya-Hsiu Lin | 2020-08-11 |
| 10665585 | Structure and method for alignment marks | Chun-Kuang Chen, Hsien-Cheng Wang | 2020-05-26 |
| 10651030 | Cut metal gate process for reducing transistor spacing | Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen | 2020-05-12 |
| 10461078 | Creating devices with multiple threshold voltage by cut-metal-gate process | Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin | 2019-10-29 |
| 10319581 | Cut metal gate process for reducing transistor spacing | Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen | 2019-06-11 |
| 10163738 | Structure and method for overlay marks | Hsien-Cheng Wang, Chun-Kuang Chen, Yao-Ching Ku | 2018-12-25 |
| 9543406 | Structure and method for overlay marks | Hsien-Cheng Wang, Chun-Kuang Chen, Yao-Ching Ku | 2017-01-10 |
| 9280041 | Cross quadrupole double lithography method using two complementary apertures | Hsien-Cheng Wang, Hung-Chang Hsieh, Shih-Che Wang, Ping-Chieh Wu, Wen-Chun Huang | 2016-03-08 |
| 9000525 | Structure and method for alignment marks | Hsien-Cheng Wang, Chun-Kuang Chen | 2015-04-07 |
| 8416393 | Cross quadrupole double lithography method and apparatus for semiconductor device fabrication using two apertures | Hsien-Cheng Wang, Hung-Chang Hsieh, Shih-Che Wang, Ping-Chieh Wu, Wen-Chun Huang | 2013-04-09 |
| 7649024 | Process for preparing nanofluids with rotating packed bed reactor | Chia-Chen Li, Mu-Jen Young, Ruey-Fu Shih, Meu-Hui Chang | 2010-01-19 |