Issued Patents All Time
Showing 101–115 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157922 | Interconnect metal layout for integrated circuit | Wei-Cheng Lin, Jiann-Tyng Tzeng, Charles Chew-Yuen Young | 2018-12-18 |
| 10109582 | Advanced metal connection with metal cut | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +6 more | 2018-10-23 |
| 10096522 | Dummy MOL removal for performance enhancement | Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +4 more | 2018-10-09 |
| 10074657 | Method of manufacturing fins and semiconductor device which includes fins | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng +3 more | 2018-09-11 |
| 10032759 | High-density semiconductor device | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Ru-Gun Liu +2 more | 2018-07-24 |
| 9917050 | Semiconductor device including source/drain contact having height below gate stack | Chih-Liang Chen, Chih-Ming Lai, Ru-Gun Liu, Meng-Hung Shen, Chun-Hung Liou +2 more | 2018-03-13 |
| 9911697 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng +6 more | 2018-03-06 |
| 9837353 | Middle end-of-line strap for standard cell | Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2017-12-05 |
| 9793211 | Dual power structure with connection pins | Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2017-10-17 |
| 9754881 | Designed-based interconnect structure in semiconductor structure | Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Tsong-Hua Ou, Chun-Kuang Chen +3 more | 2017-09-05 |
| 9679994 | High fin cut fabrication process | L. C. Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng +3 more | 2017-06-13 |
| 9478636 | Method of forming semiconductor device including source/drain contact having height below gate stack | Chih-Liang Chen, Chih-Ming Lai, Ru-Gun Liu, Meng-Hung Shen, Chun-Hung Liou +2 more | 2016-10-25 |
| 9281273 | Designed-based interconnect structure in semiconductor structure | Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Tsong-Hua Ou, Chun-Kuang Chen +3 more | 2016-03-08 |
| 9184250 | Semiconductor arrangement and formation thereof | Chih-Liang Chen, Helen Shu-Hui Chang, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2015-11-10 |
| 8698205 | Integrated circuit layout having mixed track standard cell | Jiann-Tyng Tzeng, Chih-Liang Chen, Yi-Feng James Chen, Shang-Chih Hsieh, Helen Shu-Hui Chang | 2014-04-15 |