Issued Patents All Time
Showing 676–700 of 719 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6239458 | Polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two polysilicon layer load resistor | Jin-Yuan Lee | 2001-05-29 |
| 6228731 | Re-etched spacer process for a self-aligned structure | Yun-Hung Shen | 2001-05-08 |
| 6228726 | Method to suppress CMOS device latchup and improve interwell isolation | — | 2001-05-08 |
| 6214656 | Partial silicide gate in sac (self-aligned contact) process | — | 2001-04-10 |
| 6214698 | Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer | Jin-Yuan Lee, Kuei-Ying Lee, Chu-Yun Fu, Kong-Beng Thei | 2001-04-10 |
| 6180530 | Self-aligned contact structure | Jin-Yuan Lee | 2001-01-30 |
| 6177338 | Two step barrier process | Ching-Yau Yang | 2001-01-23 |
| 6174775 | Method for making a dual gate structure for CMOS device | — | 2001-01-16 |
| 6172411 | Self-aligned contact structures using high selectivity etching | Li-Chih Chao, Yuan-Chang Huang, Jin-Yuan Lee | 2001-01-09 |
| 6121684 | Integrated butt contact having a protective spacer | — | 2000-09-19 |
| 6090674 | Method of forming a hole in the sub quarter micron range | Hung-Chang Hsieh, Hua-Tai Lin, Jin-Yuan Lee | 2000-07-18 |
| 6080647 | Process to form a trench-free buried contact | Kuo-Ching Huang, Yean-Kuen Fang, Mong-Song Liang, Cheng-Ming Wu, Dun-Nian Yaung | 2000-06-27 |
| 6071798 | Method for fabricating buried contacts | Dun-Nian Yaung, Shou-Gwo Wuu, Jin-Yuan Lee | 2000-06-06 |
| 6063711 | High selectivity etching stop layer for damascene process | Li-Chih Chao, Chia-Shiung Tsai, Chu-Yun Fu | 2000-05-16 |
| 6020267 | Method for forming local interconnect metal structures via the addition of a titanium nitride anti-reflective coating | Ching-Yau Yang | 2000-02-01 |
| 6013547 | Process for creating a butt contact opening for a self-aligned contact structure | — | 2000-01-11 |
| 5998249 | Static random access memory design and fabrication process featuring dual self-aligned contact structures | Jin-Yuan Lee | 1999-12-07 |
| 5986328 | Buried contact architecture | — | 1999-11-16 |
| 5972759 | Method of making an integrated butt contact having a protective spacer | — | 1999-10-26 |
| 5970346 | Fuse window guard ring structure for nitride capped self aligned contact processes | — | 1999-10-19 |
| 5960276 | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process | Dun-Nian Yaung, Jin-Yuan Lee | 1999-09-28 |
| 5955768 | Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell | Jin-Yuan Lee | 1999-09-21 |
| 5930633 | Integrated butt-contact process in shallow trench isolation | — | 1999-07-27 |
| 5926706 | Method for making a trench-free buried contact with low resistance on semiconductor integrated circuits | Jin-Yuan Lee | 1999-07-20 |
| 5926728 | Method for fabricating tungsten polycide contacts | Hsiang-Fan Lee, Yi-Miaw Lin, Liang Szuma | 1999-07-20 |